* RX/TX swap on clock active (two drivers)

* This module now only contains 10GbE configured for comcellnode.
* Also bring correction for synthesis

* Ethernet core is now 'comcellnode_ethernet_core'.
* Drop all capitals letters in addrespace name.

* Not tested

* Move integration of ethernet IP to comcellnode_ethernet.
* New top level file that integrate ethernet and packeter.
* Need AXI-MM logic.

* Not synthesized yet
* Well tested, need to automate and do special cases

* Tested via simulation
* still no header insertion

* OK for one sequence
* No timeout yet
* No new features

* Only Sequence detector and frame counter
* No header insertion yet
* Not simulated, not synthesized

* Change the External data path on GT wizard settings
* tie the loopback to top level
* bring the usrclk2 out to the top level