Skip to content
Snippets Groups Projects
Commit d2612317 authored by BRONES Romain's avatar BRONES Romain
Browse files

WIP Add timeout feature 

* Tested via simulation
* still no header insertion
parent e7c1ed7a
Branches
Tags
No related merge requests found
Show whitespace changes
Inline Side-by-side
hdl/comcellnode_packeter.vhd
+ 53
− 4
View file @ d2612317
......@@ -32,11 +32,17 @@ entity comcellnode_packeter is
-- Control
packeter_run : in std_logic;
-- Status
status_err_seq : out std_logic;
status_err_timeout : out std_logic;
status_packet_count : out std_logic_vector(31 downto 0);
-- Configuration
mac_dst : in std_logic_vector(47 downto 0);
mac_src : in std_logic_vector(47 downto 0);
mac_length : in std_logic_vector(15 downto 0);
bpmframe_timeout : in std_logic_vector(15 downto 0);
bpm_frame_cnt : in std_logic_vector(7 downto 0);
timeref : in std_logic_vector(63 downto 0)
);
......@@ -88,6 +94,10 @@ architecture rtl of comcellnode_packeter is
signal frame_timeout : std_logic;
signal m_tvalid_r : std_logic;
signal timeout_cnt : unsigned(15 downto 0);
signal packet_counter : unsigned(31 downto 0);
begin
......@@ -183,13 +193,52 @@ begin
);
-------------
-- TIMEOUT --
-------------
p_timeout:process(aclk, aresetn)
begin
if aresetn = '0' then
timeout_cnt <= (others => '0');
elsif rising_edge(aclk) then
if fsm_state = RUN then
timeout_cnt <= timeout_cnt - 1;
else
timeout_cnt <= unsigned(bpmframe_timeout);
end if;
end if;
end process p_timeout;
frame_timeout <= '1' when timeout_cnt = 0 else '0';
--------------------
-- PACKET COUNTER --
--------------------
p_pckt_cnt:process(aclk, aresetn)
begin
if aresetn = '0' then
packet_counter <= (others => '0');
elsif rising_edge(aclk) then
if packeter_run = '0' then
packet_counter <= (others => '0');
else
if fsm_state = FIRST then
packet_counter <= packet_counter+1;
end if;
end if;
end if;
end process p_pckt_cnt;
------------
-- STATUS --
------------
status_err_seq <= '1' when fsm_state = ERR_SEQ else '0';
status_err_timeout <= '1' when fsm_state = ERR_TO else '0';
status_packet_count <= std_logic_vector(packet_counter);
---------
-- FSM --
---------
-- temporary
frame_timeout <= '0';
p_fsm_sync:process(aclk, aresetn)
begin
if aresetn = '0' then
......
sim/tb_comcellnode_packeter.vhd
+ 119
− 63
View file @ d2612317
......@@ -43,6 +43,10 @@ architecture testbench of tb_comcellnode_packeter is
signal tb_mac_dst : std_logic_vector(47 downto 0);
signal tb_mac_src : std_logic_vector(47 downto 0);
signal tb_mac_length : std_logic_vector(15 downto 0);
signal tb_status_err_seq : std_logic;
signal tb_status_err_timeout : std_logic;
signal tb_status_packet_count : std_logic_vector(31 downto 0);
signal tb_bpmframe_timeout : std_logic_vector(15 downto 0);
signal tx_send : boolean := false;
signal rx_recv : boolean := false;
......@@ -84,6 +88,10 @@ begin
m_axis_tuser => tb_m_axis_tuser,
packeter_run => tb_packeter_run,
status_err_seq => tb_status_err_seq,
status_err_timeout => tb_status_err_timeout,
status_packet_count => tb_status_packet_count,
bpmframe_timeout => tb_bpmframe_timeout,
mac_dst => tb_mac_dst,
mac_src => tb_mac_src,
......@@ -121,6 +129,7 @@ begin
tb_mac_src <= (others => '0');
tb_mac_length <= (others => '0');
tb_packeter_run <= '1';
tb_bpmframe_timeout <= x"0040";
wait for 40 ns;
wait until rising_edge(tb_clk);
tb_rstn <= '1';
......@@ -130,6 +139,7 @@ begin
wait until rising_edge(tb_clk);
end loop;
-- Configuration values
tb_mac_dst <= x"010000DBAAFF";
tb_mac_src <= x"050000DBAAFF";
......@@ -137,6 +147,9 @@ begin
tb_mac_length <= x"003A"; -- 58 Bytes: 5 BPM frames
wait until rising_edge(tb_clk);
-- Enable RX after a time
rx_recv <= true after 1 us;
-- Send some BPM frames
fa_seq <= x"01";
tx_send <= true;
......@@ -144,14 +157,57 @@ begin
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence
-- New sequence, with more frame than expected
fa_seq <= x"02";
for I in 0 to 8 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence, with just the number of frame as expected
fa_seq <= x"03";
for I in 0 to 5 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence, with fewer frame than expected
fa_seq <= x"04";
for I in 0 to 2 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence, won't be taken
fa_seq <= x"05";
for I in 0 to 5 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence, with more frame than expected
fa_seq <= x"06";
for I in 0 to 8 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- New sequence, stall
fa_seq <= x"07";
for I in 0 to 2 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
tx_send <= false;
wait for 1.5 us;
tx_send <= true;
-- New sequence
fa_seq <= x"08";
for I in 0 to 5 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- Enable RX
rx_recv <= true;
-- New sequence
fa_seq <= x"09";
for I in 0 to 5 loop
wait until rising_edge(tb_clk) and tb_s_axis_tready = '1';
end loop;
-- Never ending end
wait;
......
sim/tb_comcellnode_packeter.wcfg
+ 27
− 6
View file @ d2612317
......@@ -12,15 +12,15 @@
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="1434782fs"></ZoomStartTime>
<ZoomEndTime time="1641052fs"></ZoomEndTime>
<Cursor1Time time="1559151fs"></Cursor1Time>
<ZoomStartTime time="0fs"></ZoomStartTime>
<ZoomEndTime time="6000001fs"></ZoomEndTime>
<Cursor1Time time="6000000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="245"></NameColumnWidth>
<ValueColumnWidth column_width="262"></ValueColumnWidth>
<ValueColumnWidth column_width="258"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="10" />
<WVObjectSize size="11" />
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_clk">
<obj_property name="ElementShortName">tb_clk</obj_property>
<obj_property name="ObjectShortName">tb_clk</obj_property>
......@@ -29,6 +29,23 @@
<obj_property name="ElementShortName">tb_rstn</obj_property>
<obj_property name="ObjectShortName">tb_rstn</obj_property>
</wvobject>
<wvobject type="group" fp_name="group76">
<obj_property name="label">Status</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/status_err_seq">
<obj_property name="ElementShortName">status_err_seq</obj_property>
<obj_property name="ObjectShortName">status_err_seq</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/status_err_timeout">
<obj_property name="ElementShortName">status_err_timeout</obj_property>
<obj_property name="ObjectShortName">status_err_timeout</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/status_packet_count">
<obj_property name="ElementShortName">status_packet_count[31:0]</obj_property>
<obj_property name="ObjectShortName">status_packet_count[31:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group141">
<obj_property name="label">Config</obj_property>
<obj_property name="DisplayName">label</obj_property>
......@@ -168,7 +185,7 @@
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group148">
<obj_property name="label">Frame Cnt</obj_property>
<obj_property name="label">Frame Cnt &amp; timeout</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/frame_cnt">
......@@ -179,6 +196,10 @@
<obj_property name="ElementShortName">frame_cnt_zero</obj_property>
<obj_property name="ObjectShortName">frame_cnt_zero</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/timeout_cnt">
<obj_property name="ElementShortName">timeout_cnt[15:0]</obj_property>
<obj_property name="ObjectShortName">timeout_cnt[15:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group150">
<obj_property name="label">New Seq</obj_property>
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment

The place to be for your source code