Invert GT ResetDone before feeding eth subsystem

hdl/top_comcellnode.vhd

@@ -298,6 +298,8 @@ architecture struct of top_comcellnode is
     signal rxdata           : std_logic_vector(127 downto 0);
     signal rxrstdone        : std_logic;
     signal txrstdone        : std_logic;
+    signal rxrstdone_n      : std_logic;
+    signal txrstdone_n      : std_logic;
     signal gtloopback       : std_logic;
 
     signal txunderflow      : std_logic;
@@ -305,6 +307,9 @@ architecture struct of top_comcellnode is
 
 begin
 
+    rxrstdone_n <= not rxrstdone;
+    txrstdone_n <= not txrstdone;
+
     sfp_tx_disable  <= '0';
     rx_los  <= sfp_rx_los;
     mod_abs <= sfp_mod_abs;
@@ -384,14 +389,14 @@ begin
         s_axi_aresetn_0                  => rst_n,
 
         -- GT reset
-        rx_reset_0                       => rxrstdone,
-        tx_reset_0                       => txrstdone,
+        rx_reset_0                       => rxrstdone_n,
+        tx_reset_0                       => txrstdone_n,
         gtwiz_reset_tx_done_0            => txrstdone,
         gtwiz_reset_rx_done_0            => rxrstdone,
         ctl_gt_reset_all_0               => gt_rst_all,
         ctl_gt_tx_reset_0                => gt_rst_tx,
         ctl_gt_rx_reset_0                => gt_rst_rx,
-        rx_serdes_reset_0                => rxrstdone,
+        rx_serdes_reset_0                => rxrstdone_n,
 
         -- Clocks
         rx_serdes_clk_0                  => rxusrclk2,