Skip to content
Snippets Groups Projects
Commit b9c1a94b authored by BRONES Romain's avatar BRONES Romain
Browse files

Connect AXI-MM in top level

parent 344ef98e
Branches
Tags
No related merge requests found
Show whitespace changes
Inline Side-by-side
hdl/top_comcellnode.vhd
+ 106
− 104
View file @ b9c1a94b
......@@ -2,6 +2,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library desyrdl;
use desyrdl.common.all;
use desyrdl.pkg_comcellnode.all;
entity top_comcellnode is
port(
......@@ -12,7 +15,7 @@ entity top_comcellnode is
free_100_clk : in std_logic;
-- Running timeref
timeref : in std_logic_vector(63 downto 0)
timeref : in std_logic_vector(63 downto 0);
-- Common Quad signals
qpll0clk_in : in std_logic;
......@@ -22,6 +25,8 @@ entity top_comcellnode is
-- AXI-MM Status and Config
aclk : in std_logic;
pi_s_top : in t_comcellnode_m2s;
po_s_top : out t_comcellnode_s2m;
-- AXIS BPM com input
s_axis_clk : in std_logic;
......@@ -45,7 +50,7 @@ entity top_comcellnode is
sfp_rx_los : in std_logic;
sfp_mod_abs : in std_logic;
sfp_tx_disable : out std_logic;
sfp_tx_fault : in std_logic;
sfp_tx_fault : in std_logic
);
end entity top_comcellnode;
......@@ -72,33 +77,28 @@ architecture rtl of top_comcellnode is
signal eth_axis_rx_tkeep : std_logic_vector(7 downto 0);
signal eth_axis_rx_tdata : std_logic_vector(63 downto 0);
signal tx_clk_rst : std_logic;
signal rx_clk_rst : std_logic;
signal tx_data_rst : std_logic;
signal rx_data_rst : std_logic;
signal tx_rst : std_logic;
signal rx_rst : std_logic;
signal gt_loopback : std_logic_vector(2 downto 0);
signal tx_clk_active : std_logic;
signal rx_clk_active : std_logic;
signal gt_powergood : std_logic;
signal cdr_stable : std_logic;
signal rx_los : std_logic;
signal mod_abs : std_logic;
signal tx_fault : std_logic;
signal status_err_seq : std_logic;
signal status_err_timeout : std_logic;
signal status_packet_count : std_logic_vector(31 downto 0);
signal packeter_run : std_logic;
signal mac_dst : std_logic_vector(47 downto 0);
signal mac_src : std_logic_vector(47 downto 0);
signal mac_length : std_logic_vector(15 downto 0);
signal bpmframe_timeout : std_logic_vector(15 downto 0);
signal bpm_frame_cnt : std_logic_vector(7 downto 0);
signal addrmap_w : t_addrmap_cellnode_in;
signal addrmap_r : t_addrmap_cellnode_out;
begin
----------------------
-- AXI-MM INTERFACE --
----------------------
inst_aximm: entity desyrdl.comcellnode
port map(
pi_clock => aclk,
pi_reset => aresetn,
pi_s_top => pi_s_top,
po_s_top => po_s_top,
pi_addrmap => addrmap_i,
po_addrmap => addrmap_o
);
---------------------------
-- COM CELLNODE PACKETER --
---------------------------
......@@ -128,21 +128,23 @@ begin
m_axis_tuser => eth_axis_tx_tuser,
-- Status
status_err_seq => status_err_seq,
status_err_timeout => status_err_timeout,
status_packet_count => status_packet_count,
status_err_seq => addrmap_i.packeter_error.sequence,
status_err_timeout => addrmap_i.packeter_error.timeout,
status_packet_count => addrmap_i.packeter_count.count,
-- Configuration
packeter_run => packeter_run,
packeter_run => addrmap_o.packeter_bpm_frame.run,
mac_dst => mac_dst,
mac_src => mac_src,
mac_length => mac_length,
bpmframe_timeout => bpmframe_timeout,
bpm_frame_cnt => bpm_frame_cnt,
mac_length => addrmap_o.mac_length.length,
bpmframe_timeout => addrmap_o.packeter_bpm_frame.timeout,
bpm_frame_cnt => addrmap_o.packeter_bpm_frame.count,
timeref => timeref
);
mac_dst <= addrmap_o.max_dst_msb & addrmap_o.max_dst_lsb;
mac_src <= addrmap_o.max_src_msb & addrmap_o.max_src_lsb;
--------------
-- ETHERNET --
......@@ -159,13 +161,13 @@ begin
qpll0lock_in => qpll0lock_in,
qpll0reset_out => qpll0reset_out,
tx_clk_rst => tx_clk_rst,
rx_clk_rst => rx_clk_rst,
tx_data_rst => tx_data_rst,
rx_data_rst => rx_data_rst,
tx_rst => tx_rst,
rx_rst => rx_rst,
gt_loopback => gt_loopback,
tx_clk_rst => addrmap_o.eth_gt_control.rst_tx_clk,
rx_clk_rst => addrmap_o.eth_gt_control.rst_rx_clk,
tx_data_rst => addrmap_o.eth_gt_control.rst_tx_data,
rx_data_rst => addrmap_o.eth_gt_control.rst_rx_data,
tx_rst => addrmap_o.eth_gt_control.tx_clk,
rx_rst => addrmap_o.eth_gt_control.rx_clk,
gt_loopback => addrmap_o.eth_gt_control.loopback,
gt_rx_out_clk => open,
gt_tx_out_clk => open,
......@@ -180,13 +182,13 @@ begin
sfp_tx_fault => sfp_tx_fault,
-- Status
tx_clk_active => tx_clk_active,
rx_clk_active => rx_clk_active,
gt_powergood => gt_powergood,
cdr_stable => cdr_stable,
rx_los => rx_los,
mod_abs => mod_abs,
tx_fault => tx_fault,
tx_clk_active => addrmap_i.eth_gt_status.tx_clk_active,
rx_clk_active => addrmap_i.eth_gt_status.tx_clk_active,
gt_powergood => addrmap_i.eth_gt_status.powergood,
cdr_stable => addrmap_i.eth_gt_status.cdr_stable,
rx_los => addrmap_i.eth_gt_status.sfp_rx_los,
mod_abs => addrmap_i.eth_gt_status.sfp_mod_abs,
tx_fault => addrmap_i.eth_gt_status.sfp_tx_fault,
-- AXIS
rx_axis_tvalid => eth_axis_rx_tvalid,
......@@ -203,23 +205,23 @@ begin
tx_axis_tuser => eth_axis_tx_tuser,
-- AXI MM
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
s_axi_awaddr => addrmap_o.eth.awaddr(11 downto 0),
s_axi_awvalid => addrmap_o.eth.awvalid,
s_axi_awready => addrmap_i.eth.awready,
s_axi_wdata => addrmap_o.eth.wdata,
s_axi_wstrb => addrmap_o.eth.wsrtb,
s_axi_wvalid => addrmap_o.eth.wvalid,
s_axi_wready => addrmap_i.eth.wready,
s_axi_bresp => addrmap_i.eth.bresp,
s_axi_bvalid => addrmap_i.eth.bvalid,
s_axi_bready => addrmap_o.eth.bready,
s_axi_araddr => addrmap_o.eth.araddr(11 DOWNTO 0),
s_axi_arvalid => addrmap_o.eth.arvalid,
s_axi_arready => addrmap_i.eth.arready,
s_axi_rdata => addrmap_i.eth.rdata,
s_axi_rresp => addrmap_i.eth.rresp,
s_axi_rvalid => addrmap_i.eth.rvalid,
s_axi_rready => addrmap_o.eth.rready
);
......
rdl/comcellnode.rdl
+ 3
− 0
View file @ b9c1a94b
......@@ -57,6 +57,9 @@ addrmap COMCELLNODE {
field {hw=w; sw=r;} SFP_RX_LOS;
field {hw=w; sw=r;} SFP_MOD_ABS;
field {hw=w; sw=r;} SFP_TX_FAULT;
field {hw=w; sw=r;} TX_CLK_ACTIVE;
field {hw=w; sw=r;} RX_CLK_ACTIVE;
field {hw=w; sw=r;} POWERGOOD;
} ETH_GT_STATUS;
};
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment

The place to be for your source code