Correction on addressmap and RDL

rdl/comcellnode.rdl

-`include "comcellnode.vh" // Auto generated by FWK
-
 
 addrmap COMCELLNODE {
 

rdl/xilinx_ethsubsyst.rdl

 addrmap xil_ethsubsyst {
+
+    desyrdl_generate_hdl = false;
+    desyrdl_interface = "AXI4L";
+
 //===================
 	reg {
 		field {

tcl/main.tcl

@@ -30,7 +30,7 @@ proc setSources {} {
 proc setAddressSpace {} {
     variable AddressSpace
     addAddressSpace AddressSpace "COMCELLNODE" RDL {} ../rdl/comcellnode.rdl
-    addAddressSpace AddressSpace "xil_ethsubsyst" RDL {} ../rdl/xil_ethsubsyst.rdl
+    addAddressSpace AddressSpace "xil_ethsubsyst" RDL {} ../rdl/xilinx_ethsubsyst.rdl
 }
 
 # ==============================================================================
@@ -45,8 +45,9 @@ proc doOnCreate {} {
   set_property part ${fpga_part} [current_project]
   set_property target_language VHDL [current_project]
 
-  # Create GT wizard IP
-  source ../tcl/combpm_gtwizard.tcl
+  # 
+  source ../tcl/generate_ethernet.tcl
+  source ../tcl/generate_axisinterco.tcl
 }
 
 # ==============================================================================