Add Reset Helper to handle the reset sequence

Makefile

@@ -14,9 +14,11 @@ hdlpkgsrc :=
 rdlsrc := $(shell ls rdl/*.rdl)
 rdltarget := $(rdlsrc:rdl/%.rdl=hdl/%.vhd)
 hdlsrc := $(shell ls hdl/*.vhd) $(rdltarget) $(hdlpkgsrc)
+vlogsrc := $(shell ls hdl/*.v)
 # TODO: depends on the configuration
 tcl/sources.tcl:
 	echo read_vhdl {$(hdlsrc)} > $@
+	echo read_verilog {$(vlogsrc)} >> $@
 
 ###############################################################################
 # Compute interface from rdl files

hdl/comcellnode_ethernet_reset_wrapper.v

+// ------------------------------------------------------------------------------
+//   (c) Copyright 2020-2021 Xilinx, Inc. All rights reserved.
+// 
+//   This file contains confidential and proprietary information
+//   of Xilinx, Inc. and is protected under U.S. and
+//   international copyright and other intellectual property
+//   laws.
+// 
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+// 
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+//   Applications\"). Customer assumes the sole risk and
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+// 
+//   THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+//   PART OF THIS FILE AT ALL TIMES.
+//
+// 
+//
+//       Owner:          
+//       Revision:       $Id: $
+//                       $Author: $
+//                       $DateTime: $
+//                       $Change: $
+//       Description:
+//
+// 
+////------------------------------------------------------------------------------
+
+`timescale 1ps / 1ps
+(* DowngradeIPIdentifiedWarnings="yes" *)
+module comcellnode_ethernet_reset_wrapper
+(
+    input  wire sys_reset,
+    input  wire dclk,
+    input  wire s_axi_aclk,
+    input  wire ctl_gt_reset_all,
+    input  wire ctl_gt_tx_reset,
+    input  wire ctl_gt_rx_reset,
+    input wire gtwiz_reset_tx_datapath,
+    input wire gtwiz_reset_rx_datapath,
+    input  wire gt_txusrclk2,
+    input  wire gt_rxusrclk2,
+    input  wire rx_core_clk,
+    input  wire gt_tx_reset_in,
+    input  wire gt_rx_reset_in,
+
+    input  wire tx_core_reset_in,
+    input  wire rx_core_reset_in,
+    output wire tx_core_reset_out,
+    output wire rx_core_reset_out,
+    output wire rx_serdes_reset_out,
+    output wire usr_tx_reset,
+    output wire usr_rx_reset,
+    output wire gtwiz_reset_all,
+    output wire gtwiz_reset_tx_datapath_out,
+    output wire gtwiz_reset_rx_datapath_out
+);
+
+  wire gt_tx_reset_in_sync;
+  wire gt_tx_reset_in_sync_inv;
+  wire tx_reset_done_async;
+
+  wire gt_rx_reset_in_sync;
+  wire gt_rx_reset_in_sync_inv;
+  wire rx_reset_done_async;
+  wire rx_serdes_reset_done;
+  reg  rx_reset_done_async_r;
+  wire rx_reset_done;
+
+
+  reg  ctl_gt_reset_all_r;
+  wire ctl_gt_reset_all_sync; 
+
+  always @( posedge s_axi_aclk)
+  begin
+       ctl_gt_reset_all_r  <= ctl_gt_reset_all;
+  end
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_core_cdc_sync_axi_gt_resetall
+  (
+   .clk              (dclk),
+   .signal_in        (ctl_gt_reset_all_r), 
+   .signal_out       (ctl_gt_reset_all_sync)
+  );
+
+  reg  ctl_gt_tx_reset_r;
+  wire ctl_gt_tx_reset_sync; 
+
+  always @( posedge s_axi_aclk)
+  begin
+       ctl_gt_tx_reset_r  <= ctl_gt_tx_reset;
+  end
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_core_cdc_sync_axi_ctl_gt_tx_reset
+  (
+   .clk              (dclk),
+   .signal_in        (ctl_gt_tx_reset_r), 
+   .signal_out       (ctl_gt_tx_reset_sync)
+  );
+
+  reg  ctl_gt_rx_reset_r;
+  wire ctl_gt_rx_reset_sync; 
+
+  always @( posedge s_axi_aclk)
+  begin
+       ctl_gt_rx_reset_r  <= ctl_gt_rx_reset;
+  end
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_core_cdc_sync_axi_ctl_gt_rx_reset
+  (
+   .clk              (dclk),
+   .signal_in        (ctl_gt_rx_reset_r), 
+   .signal_out       (ctl_gt_rx_reset_sync)
+  );
+
+
+  assign gtwiz_reset_tx_datapath_out = gtwiz_reset_tx_datapath | ctl_gt_tx_reset_sync;
+  assign gtwiz_reset_rx_datapath_out = gtwiz_reset_rx_datapath | ctl_gt_rx_reset_sync;
+
+  assign gtwiz_reset_all             = sys_reset | ctl_gt_reset_all_sync;
+ 
+ 
+
+ 
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_cdc_sync_gt_tx_resetdone
+  (
+   .clk              (gt_txusrclk2),
+   .signal_in        (gt_tx_reset_in), 
+   .signal_out       (gt_tx_reset_in_sync)
+  );
+
+  assign gt_tx_reset_in_sync_inv  =  ~(gt_tx_reset_in_sync);
+  assign tx_reset_done_async      =  gt_tx_reset_in_sync_inv | tx_core_reset_in;
+  assign usr_tx_reset             =  tx_reset_done_async;
+  assign tx_core_reset_out        =  tx_reset_done_async;
+
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_cdc_sync_gt_rx_resetdone
+  (
+   .clk              (gt_txusrclk2),
+   .signal_in        (gt_rx_reset_in), 
+   .signal_out       (gt_rx_reset_in_sync)
+  );
+
+  assign gt_rx_reset_in_sync_inv   =  ~(gt_rx_reset_in_sync);
+  assign rx_reset_done_async       =  gt_rx_reset_in_sync_inv | rx_core_reset_in;
+ 
+  always @( posedge gt_txusrclk2)
+  begin
+       rx_reset_done_async_r  <= rx_reset_done_async;
+  end
+ 
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_cdc_sync_gt_rx_serdes_resetdone
+  (
+   .clk              (gt_rxusrclk2),
+   .signal_in        (rx_reset_done_async_r), 
+   .signal_out       (rx_serdes_reset_done)
+  );
+ 
+  comcellnode_ethernet_reset_wrapper_cdc_sync i_comcellnode_ethernet_cdc_sync_gt_rx_resetdone_rx_core_clk
+  (
+   .clk              (rx_core_clk),
+   .signal_in        (rx_reset_done_async_r), 
+   .signal_out       (rx_reset_done)
+  );
+ 
+  assign rx_serdes_reset_out        = rx_serdes_reset_done;
+  assign rx_core_reset_out          = rx_reset_done;
+  assign usr_rx_reset               = rx_reset_done;
+
+endmodule
+
+
+(* DowngradeIPIdentifiedWarnings="yes" *)
+  module comcellnode_ethernet_reset_wrapper_cdc_sync (
+   input clk,
+   input signal_in,
+   output wire signal_out
+  );
+  
+                                wire sig_in_cdc_from ;
+       (* ASYNC_REG = "TRUE" *) reg  s_out_d2_cdc_to;
+       (* ASYNC_REG = "TRUE" *) reg  s_out_d3;
+       (* ASYNC_REG = "TRUE" *) reg  s_out_d4;
+      
+// synthesis translate_off
+      
+      initial s_out_d2_cdc_to = 1'b0;
+      initial s_out_d3        = 1'b0;
+      initial s_out_d4        = 1'b0;
+      
+// synthesis translate_on   
+
+      assign sig_in_cdc_from = signal_in;
+      assign signal_out      = s_out_d4;
+
+      always @(posedge clk) 
+      begin
+        s_out_d2_cdc_to  <= sig_in_cdc_from;
+        s_out_d3         <= s_out_d2_cdc_to;
+        s_out_d4         <= s_out_d3;
+      end
+  
+  endmodule
+

hdl/top_comcellnode.vhd

@@ -13,6 +13,13 @@ entity top_comcellnode is
         qpll0lock_in                       : in std_logic;
         qpll0reset_out                     : out std_logic;
 
+        tx_clk_rst                         : in std_logic;
+        rx_clk_rst                         : in std_logic;
+        tx_data_rst                        : in std_logic;
+        rx_data_rst                        : in std_logic;
+        tx_rst                             : in std_logic;
+        rx_rst                             : in std_logic;
+
         -- SFP signals
         sfp_rxn                            : in std_logic;
         sfp_rxp                            : in std_logic;
@@ -30,6 +37,7 @@ entity top_comcellnode is
         cdr_stable                         : out std_logic;
         rx_los                             : out std_logic;
         mod_abs                            : out std_logic;
+        tx_fault                           : out std_logic;
 
         -- AXIS
         rx_axis_tvalid                     : OUT STD_LOGIC;
@@ -284,22 +292,33 @@ architecture struct of top_comcellnode is
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
+    signal rst              : std_logic;
+
     signal rxgearboxslip    : std_logic;
     signal rxdatavalid      : std_logic_vector(1 downto 0);
     signal rxheader         : std_logic_vector(5 downto 0);
     signal txheader         : std_logic_vector(5 downto 0);
     signal rxheadervalid    : std_logic_vector(1 downto 0);
+
     signal gt_rst_all       : std_logic;
     signal gt_rst_tx        : std_logic;
     signal gt_rst_rx        : std_logic;
+    signal gtwiz_reset_all  : std_logic;
+    signal rx_serdes_rst    : std_logic;
+
+    signal gtwiz_rst_tx_datapath : std_logic;
+    signal gtwiz_rst_rx_datapath : std_logic;
+
+    signal gtwiz_tx_rst_done : std_logic;
+    signal gtwiz_rx_rst_done : std_logic;
+
+    signal rx_rst_core      : std_logic;
+    signal tx_rst_core      : std_logic;
+
     signal rxusrclk2        : std_logic;
     signal main_clk         : std_logic;
     signal txdata           : std_logic_vector(127 downto 0);
     signal rxdata           : std_logic_vector(127 downto 0);
-    signal rxrstdone        : std_logic;
-    signal txrstdone        : std_logic;
-    signal rxrstdone_n      : std_logic;
-    signal txrstdone_n      : std_logic;
     signal gtloopback       : std_logic;
 
     signal txunderflow      : std_logic;
@@ -307,24 +326,26 @@ architecture struct of top_comcellnode is
 
 begin
 
-    rxrstdone_n <= not rxrstdone;
-    txrstdone_n <= not txrstdone;
+    rst <= not rst_n;
 
     sfp_tx_disable  <= '0';
     rx_los  <= sfp_rx_los;
     mod_abs <= sfp_mod_abs;
+    tx_fault <= sfp_tx_fault;
 
     axis_clk        <= main_clk;
 
     inst_gtwizard:comcellnode_gtwizard
     PORT map(
 
-        -- Async Reset
-        gtwiz_reset_all_in(0)              => gt_rst_all,
-        gtwiz_userclk_rx_reset_in(0)       => gt_rst_rx,
-        gtwiz_userclk_tx_reset_in(0)       => gt_rst_tx,
-        gtwiz_reset_rx_done_out(0)         => rxrstdone,
-        gtwiz_reset_tx_done_out(0)         => txrstdone,
+        -- Reset
+        gtwiz_reset_all_in(0)              => gtwiz_reset_all,
+        gtwiz_userclk_rx_reset_in(0)       => rx_clk_rst,
+        gtwiz_userclk_tx_reset_in(0)       => tx_clk_rst,
+        gtwiz_reset_tx_done_out(0)         => gtwiz_tx_rst_done,
+        gtwiz_reset_rx_done_out(0)         => gtwiz_rx_rst_done,
+        gtwiz_reset_tx_datapath_in(0)      => gtwiz_rst_tx_datapath,
+        gtwiz_reset_rx_datapath_in         => gtwiz_rst_rx_datapath,
 
         -- Clocks
         gtwiz_userclk_rx_usrclk2_out(0)    => rxusrclk2,
@@ -368,9 +389,7 @@ begin
         -- Not used
         txsequence_in                      => (others => '0'),
         gtwiz_reset_tx_pll_and_datapath_in => "0",
-        gtwiz_reset_tx_datapath_in         => "0",
         gtwiz_reset_rx_pll_and_datapath_in => "0",
-        gtwiz_reset_rx_datapath_in         => "0",
         qpll1clk_in                        => "0",
         qpll1refclk_in                     => "0",
         gtwiz_userclk_tx_srcclk_out        => open,
@@ -389,14 +408,14 @@ begin
         s_axi_aresetn_0                  => rst_n,
 
         -- GT reset
-        rx_reset_0                       => rxrstdone_n,
-        tx_reset_0                       => txrstdone_n,
-        gtwiz_reset_tx_done_0            => txrstdone,
-        gtwiz_reset_rx_done_0            => rxrstdone,
+        rx_reset_0                       => rx_rst_core,
+        tx_reset_0                       => tx_rst_core,
+        gtwiz_reset_tx_done_0            => gtwiz_tx_rst_done,
+        gtwiz_reset_rx_done_0            => gtwiz_rx_rst_done,
         ctl_gt_reset_all_0               => gt_rst_all,
         ctl_gt_tx_reset_0                => gt_rst_tx,
         ctl_gt_rx_reset_0                => gt_rst_rx,
-        rx_serdes_reset_0                => rxrstdone_n,
+        rx_serdes_reset_0                => rx_serdes_rst,
 
         -- Clocks
         rx_serdes_clk_0                  => rxusrclk2,
@@ -537,4 +556,31 @@ begin
         stat_tx_frame_error_0            => open
     );
 
+    inst_reset_helper: entity work.comcellnode_ethernet_reset_wrapper
+    port map(
+        sys_reset                   => rst,
+        dclk                        => free_100_clk,
+        s_axi_aclk                  => axi_clk,
+        ctl_gt_reset_all            => gt_rst_all,
+        ctl_gt_tx_reset             => gt_rst_tx,
+        ctl_gt_rx_reset             => gt_rst_rx,
+        gtwiz_reset_tx_datapath     => tx_data_rst,
+        gtwiz_reset_rx_datapath     => rx_data_rst,
+        gt_txusrclk2                => main_clk,
+        gt_rxusrclk2                => rxusrclk2,
+        rx_core_clk                 => main_clk,
+        gt_tx_reset_in              => gtwiz_tx_rst_done,
+        gt_rx_reset_in              => gtwiz_rx_rst_done,
+        tx_core_reset_in            => tx_rst,
+        rx_core_reset_in            => rx_rst,
+        tx_core_reset_out           => tx_rst_core,
+        rx_core_reset_out           => rx_rst_core,
+        rx_serdes_reset_out         => rx_serdes_rst,
+        usr_tx_reset                => open,
+        usr_rx_reset                => open,
+        gtwiz_reset_all             => gtwiz_reset_all,
+        gtwiz_reset_tx_datapath_out => gtwiz_rst_tx_datapath,
+        gtwiz_reset_rx_datapath_out => gtwiz_rst_rx_datapath
+    );
+
 end architecture struct;