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Commit bc24f18a authored by BRONES Romain's avatar BRONES Romain
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Add header insertion

* Not synthesized yet
* Well tested, need to automate and do special cases
parent d2612317
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library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use ieee.std_logic_misc.or_reduce;
use work.pkg_bpmframe_stream.all; use work.pkg_bpmframe_stream.all;
...@@ -22,6 +23,7 @@ entity comcellnode_packeter is ...@@ -22,6 +23,7 @@ entity comcellnode_packeter is
s_axis_tready : out std_logic; s_axis_tready : out std_logic;
-- master interface (packet output) -- master interface (packet output)
m_clk : in std_logic;
m_axis_tvalid : out std_logic; m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic; m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(63 downto 0); m_axis_tdata : out std_logic_vector(63 downto 0);
...@@ -95,9 +97,20 @@ architecture rtl of comcellnode_packeter is ...@@ -95,9 +97,20 @@ architecture rtl of comcellnode_packeter is
signal m_tvalid_r : std_logic; signal m_tvalid_r : std_logic;
signal timeout_cnt : unsigned(15 downto 0); signal timeout_cnt : unsigned(15 downto 0);
signal packet_counter : unsigned(31 downto 0); signal packet_counter : unsigned(31 downto 0);
signal header_tvalid : std_logic;
signal header_tready : std_logic;
signal header_tdata : std_logic_vector(175 downto 0);
signal sup_arb_res_s1 : std_logic;
signal fifo_tvalid : std_logic;
signal fifo_tready : std_logic;
signal fifo_tdata : std_logic_vector(63 downto 0);
signal fifo_tkeep : std_logic_vector(7 downto 0);
signal fifo_tlast : std_logic;
signal fifo_tuser : std_logic_vector(0 downto 0);
signal fifo_tuser_slv : std_logic_vector(7 downto 0);
begin begin
...@@ -172,10 +185,6 @@ begin ...@@ -172,10 +185,6 @@ begin
bpm_wconv_s_tlast <= frame_error or frame_cnt_zero; bpm_wconv_s_tlast <= frame_error or frame_cnt_zero;
bpm_wconv_s_tuser <= (others => frame_error); bpm_wconv_s_tuser <= (others => frame_error);
-- temporary
bpm_wconv_m_tready <= m_axis_tready;
inst_wconv: entity work.axis_wconv_80_16 inst_wconv: entity work.axis_wconv_80_16
port map( port map(
aclk => aclk, aclk => aclk,
...@@ -222,7 +231,10 @@ begin ...@@ -222,7 +231,10 @@ begin
if packeter_run = '0' then if packeter_run = '0' then
packet_counter <= (others => '0'); packet_counter <= (others => '0');
else else
if fsm_state = FIRST then if (bpm_wconv_s_tvalid and
bpm_wconv_s_tready and
bpm_wconv_s_tlast and
not bpm_wconv_s_tuser(0)) = '1' then
packet_counter <= packet_counter+1; packet_counter <= packet_counter+1;
end if; end if;
end if; end if;
...@@ -236,6 +248,87 @@ begin ...@@ -236,6 +248,87 @@ begin
status_err_timeout <= '1' when fsm_state = ERR_TO else '0'; status_err_timeout <= '1' when fsm_state = ERR_TO else '0';
status_packet_count <= std_logic_vector(packet_counter); status_packet_count <= std_logic_vector(packet_counter);
----------------------
-- HEADER INSERTION --
----------------------
header_tvalid <= '1' when fsm_state = FIRST and bpm_wconv_s_tready = '1' else '0';
header_tdata(7 downto 0) <= mac_dst(47 downto 40);
header_tdata(15 downto 8) <= mac_dst(39 downto 32);
header_tdata(23 downto 16) <= mac_dst(31 downto 24);
header_tdata(31 downto 24) <= mac_dst(23 downto 16);
header_tdata(39 downto 32) <= mac_dst(15 downto 8);
header_tdata(47 downto 40) <= mac_dst(7 downto 0);
header_tdata(55 downto 48) <= mac_src(47 downto 40);
header_tdata(63 downto 56) <= mac_src(39 downto 32);
header_tdata(71 downto 64) <= mac_src(31 downto 24);
header_tdata(79 downto 72) <= mac_src(23 downto 16);
header_tdata(87 downto 80) <= mac_src(15 downto 8);
header_tdata(95 downto 88) <= mac_src(7 downto 0);
header_tdata(103 downto 96) <= mac_length(7 downto 0);
header_tdata(111 downto 104) <= mac_length(15 downto 8);
header_tdata(175 downto 112) <= timeref;
sup_arb_res_s1 <= not header_tready;
inst_interco: entity work.axis_interco_16
port map (
aclk => aclk,
aresetn => aresetn,
s00_axis_aclk => aclk,
s01_axis_aclk => aclk,
m00_axis_aclk => aclk,
s00_axis_aresetn => aresetn,
s01_axis_aresetn => aresetn,
m00_axis_aresetn => aresetn,
s00_axis_tvalid => header_tvalid,
s00_axis_tready => header_tready,
s00_axis_tdata => header_tdata,
s00_axis_tkeep => (others => '1'),
s00_axis_tlast => '0',
s00_axis_tuser => (others => '0'),
s01_axis_tvalid => bpm_wconv_m_tvalid,
s01_axis_tready => bpm_wconv_m_tready,
s01_axis_tdata => bpm_wconv_m_tdata,
s01_axis_tkeep => (others => '1'),
s01_axis_tlast => bpm_wconv_m_tlast,
s01_axis_tuser => bpm_wconv_m_tuser,
m00_axis_tvalid => fifo_tvalid,
m00_axis_tready => fifo_tready,
m00_axis_tdata => fifo_tdata,
m00_axis_tkeep => fifo_tkeep,
m00_axis_tlast => fifo_tlast,
m00_axis_tuser => fifo_tuser_slv,
s00_arb_req_suppress => '0',
s01_arb_req_suppress => sup_arb_res_s1
);
----------
-- FIFO --
----------
fifo_tuser(0) <= or_reduce(fifo_tuser_slv);
inst_fifo: entity work.axis_pkt_fifo_64
port map(
s_axis_aresetn => aresetn,
s_axis_aclk => aclk,
m_axis_aclk => m_clk,
s_axis_tvalid => fifo_tvalid,
s_axis_tready => fifo_tready,
s_axis_tdata => fifo_tdata,
s_axis_tkeep => fifo_tkeep,
s_axis_tlast => fifo_tlast,
s_axis_tuser => fifo_tuser,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tuser(0)=> m_axis_tuser
);
--------- ---------
-- FSM -- -- FSM --
--------- ---------
......
...@@ -14,12 +14,14 @@ architecture testbench of tb_comcellnode_packeter is ...@@ -14,12 +14,14 @@ architecture testbench of tb_comcellnode_packeter is
-------------------------- --------------------------
-- CONSTANT DECLARATION -- -- CONSTANT DECLARATION --
-------------------------- --------------------------
constant RX_COOLDOWN : positive := 3; constant RX_COOLDOWN : positive := 0;
constant PERIOD : time := 4 ns;
------------------------ ------------------------
-- SIGNAL DECLARATION -- -- SIGNAL DECLARATION --
------------------------ ------------------------
signal tb_clk : std_logic := '0'; signal tb_clk : std_logic := '0';
signal tb_m_clk : std_logic := '0';
signal tb_rstn : std_logic := '1'; signal tb_rstn : std_logic := '1';
signal tb_s_axis_tid : std_logic_vector(0 downto 0); signal tb_s_axis_tid : std_logic_vector(0 downto 0);
...@@ -58,13 +60,15 @@ architecture testbench of tb_comcellnode_packeter is ...@@ -58,13 +60,15 @@ architecture testbench of tb_comcellnode_packeter is
begin begin
-- clock generation -- clock generation
tb_clk <= not tb_clk after 10 ns; tb_clk <= not tb_clk after PERIOD;
tb_m_clk <= not tb_m_clk after 6.4 ns;
----------------------- -----------------------
-- DUT INSTANCIATION -- -- DUT INSTANCIATION --
----------------------- -----------------------
inst_dut: entity work.comcellnode_packeter inst_dut: entity work.comcellnode_packeter
port map( port map(
m_clk => tb_m_clk,
aclk => tb_clk, aclk => tb_clk,
aresetn => tb_rstn, aresetn => tb_rstn,
...@@ -122,15 +126,15 @@ begin ...@@ -122,15 +126,15 @@ begin
begin begin
-- let it running then reset, synchronous deassertion -- let it running then reset, synchronous deassertion
wait for 77 ns; wait for PERIOD*7+7 ns;
tb_rstn <= '0'; tb_rstn <= '0';
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
tb_mac_dst <= (others => '0'); tb_mac_dst <= (others => '0');
tb_mac_src <= (others => '0'); tb_mac_src <= (others => '0');
tb_mac_length <= (others => '0'); tb_mac_length <= (others => '0');
tb_packeter_run <= '1'; tb_packeter_run <= '1';
tb_bpmframe_timeout <= x"0040"; tb_bpmframe_timeout <= x"0060";
wait for 40 ns; wait for 4*PERIOD;
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
tb_rstn <= '1'; tb_rstn <= '1';
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
...@@ -148,7 +152,7 @@ begin ...@@ -148,7 +152,7 @@ begin
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
-- Enable RX after a time -- Enable RX after a time
rx_recv <= true after 1 us; rx_recv <= true after 50*PERIOD;
-- Send some BPM frames -- Send some BPM frames
fa_seq <= x"01"; fa_seq <= x"01";
...@@ -274,13 +278,13 @@ begin ...@@ -274,13 +278,13 @@ begin
while true loop while true loop
if not rx_recv then if not rx_recv then
tb_m_axis_tready <= '0'; tb_m_axis_tready <= '0';
wait until rx_recv and rising_edge(tb_clk); wait until rx_recv and rising_edge(tb_m_clk);
end if; end if;
tb_m_axis_tready <= '1'; tb_m_axis_tready <= '1';
wait until rising_edge(tb_clk) and tb_m_axis_tvalid ='1'; wait until rising_edge(tb_m_clk) and tb_m_axis_tvalid ='1';
tb_m_axis_tready <= '0'; tb_m_axis_tready <= '0';
for I in 0 to RX_COOLDOWN loop for I in 1 to RX_COOLDOWN loop
wait until rising_edge(tb_clk); wait until rising_edge(tb_m_clk);
end loop; end loop;
end loop; end loop;
end process p_rx_recv; end process p_rx_recv;
......
...@@ -12,15 +12,15 @@ ...@@ -12,15 +12,15 @@
</db_ref> </db_ref>
</db_ref_list> </db_ref_list>
<zoom_setting> <zoom_setting>
<ZoomStartTime time="0fs"></ZoomStartTime> <ZoomStartTime time="467760fs"></ZoomStartTime>
<ZoomEndTime time="6000001fs"></ZoomEndTime> <ZoomEndTime time="933261fs"></ZoomEndTime>
<Cursor1Time time="6000000fs"></Cursor1Time> <Cursor1Time time="662760fs"></Cursor1Time>
</zoom_setting> </zoom_setting>
<column_width_setting> <column_width_setting>
<NameColumnWidth column_width="245"></NameColumnWidth> <NameColumnWidth column_width="276"></NameColumnWidth>
<ValueColumnWidth column_width="258"></ValueColumnWidth> <ValueColumnWidth column_width="289"></ValueColumnWidth>
</column_width_setting> </column_width_setting>
<WVObjectSize size="11" /> <WVObjectSize size="13" />
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_clk"> <wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_clk">
<obj_property name="ElementShortName">tb_clk</obj_property> <obj_property name="ElementShortName">tb_clk</obj_property>
<obj_property name="ObjectShortName">tb_clk</obj_property> <obj_property name="ObjectShortName">tb_clk</obj_property>
...@@ -49,6 +49,7 @@ ...@@ -49,6 +49,7 @@
<wvobject type="group" fp_name="group141"> <wvobject type="group" fp_name="group141">
<obj_property name="label">Config</obj_property> <obj_property name="label">Config</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/packeter_run"> <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/packeter_run">
<obj_property name="ElementShortName">packeter_run</obj_property> <obj_property name="ElementShortName">packeter_run</obj_property>
<obj_property name="ObjectShortName">packeter_run</obj_property> <obj_property name="ObjectShortName">packeter_run</obj_property>
...@@ -91,7 +92,6 @@ ...@@ -91,7 +92,6 @@
<wvobject type="group" fp_name="group138"> <wvobject type="group" fp_name="group138">
<obj_property name="label">reg axis M</obj_property> <obj_property name="label">reg axis M</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_reg_m_tvalid"> <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_reg_m_tvalid">
<obj_property name="ElementShortName">bpm_reg_m_tvalid</obj_property> <obj_property name="ElementShortName">bpm_reg_m_tvalid</obj_property>
<obj_property name="ObjectShortName">bpm_reg_m_tvalid</obj_property> <obj_property name="ObjectShortName">bpm_reg_m_tvalid</obj_property>
...@@ -108,7 +108,6 @@ ...@@ -108,7 +108,6 @@
<wvobject type="group" fp_name="group137"> <wvobject type="group" fp_name="group137">
<obj_property name="label">wconv axis S</obj_property> <obj_property name="label">wconv axis S</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tvalid"> <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tvalid">
<obj_property name="ElementShortName">bpm_wconv_s_tvalid</obj_property> <obj_property name="ElementShortName">bpm_wconv_s_tvalid</obj_property>
<obj_property name="ObjectShortName">bpm_wconv_s_tvalid</obj_property> <obj_property name="ObjectShortName">bpm_wconv_s_tvalid</obj_property>
...@@ -155,6 +154,27 @@ ...@@ -155,6 +154,27 @@
<obj_property name="ObjectShortName">bpm_wconv_m_tuser[1:0]</obj_property> <obj_property name="ObjectShortName">bpm_wconv_m_tuser[1:0]</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject type="group" fp_name="group175">
<obj_property name="label">Interco</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/inst_interco/S00_AXIS_TVALID">
<obj_property name="ElementShortName">S00_AXIS_TVALID</obj_property>
<obj_property name="ObjectShortName">S00_AXIS_TVALID</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/inst_interco/S00_AXIS_TREADY">
<obj_property name="ElementShortName">S00_AXIS_TREADY</obj_property>
<obj_property name="ObjectShortName">S00_AXIS_TREADY</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/inst_interco/S01_AXIS_TVALID">
<obj_property name="ElementShortName">S01_AXIS_TVALID</obj_property>
<obj_property name="ObjectShortName">S01_AXIS_TVALID</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/inst_interco/S01_AXIS_TREADY">
<obj_property name="ElementShortName">S01_AXIS_TREADY</obj_property>
<obj_property name="ObjectShortName">S01_AXIS_TREADY</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group142"> <wvobject type="group" fp_name="group142">
<obj_property name="label">FSM</obj_property> <obj_property name="label">FSM</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
...@@ -204,6 +224,7 @@ ...@@ -204,6 +224,7 @@
<wvobject type="group" fp_name="group150"> <wvobject type="group" fp_name="group150">
<obj_property name="label">New Seq</obj_property> <obj_property name="label">New Seq</obj_property>
<obj_property name="DisplayName">label</obj_property> <obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/new_seq"> <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/new_seq">
<obj_property name="ElementShortName">new_seq</obj_property> <obj_property name="ElementShortName">new_seq</obj_property>
<obj_property name="ObjectShortName">new_seq</obj_property> <obj_property name="ObjectShortName">new_seq</obj_property>
...@@ -217,4 +238,33 @@ ...@@ -217,4 +238,33 @@
<obj_property name="ObjectShortName">new_seq_valid_r</obj_property> <obj_property name="ObjectShortName">new_seq_valid_r</obj_property>
</wvobject> </wvobject>
</wvobject> </wvobject>
<wvobject type="group" fp_name="group80">
<obj_property name="label">axis output</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tvalid">
<obj_property name="ElementShortName">m_axis_tvalid</obj_property>
<obj_property name="ObjectShortName">m_axis_tvalid</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tready">
<obj_property name="ElementShortName">m_axis_tready</obj_property>
<obj_property name="ObjectShortName">m_axis_tready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tdata">
<obj_property name="ElementShortName">m_axis_tdata[63:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tdata[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tkeep">
<obj_property name="ElementShortName">m_axis_tkeep[7:0]</obj_property>
<obj_property name="ObjectShortName">m_axis_tkeep[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tlast">
<obj_property name="ElementShortName">m_axis_tlast</obj_property>
<obj_property name="ObjectShortName">m_axis_tlast</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/m_axis_tuser">
<obj_property name="ElementShortName">m_axis_tuser</obj_property>
<obj_property name="ObjectShortName">m_axis_tuser</obj_property>
</wvobject>
</wvobject>
</wave_config> </wave_config>
# GENERATE AXI INTERCONNECT # GENERATE AXI INTERCONNECT
set xcipath [create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name comcellnode_interco] set xcipath [create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interco_16]
set_property -dict [list \ set_property -dict [list \
CONFIG.ARBITER_TYPE {Fixed} \ CONFIG.ARBITER_TYPE {Fixed} \
...@@ -8,12 +8,12 @@ set_property -dict [list \ ...@@ -8,12 +8,12 @@ set_property -dict [list \
CONFIG.C_M00_AXIS_IS_ACLK_ASYNC 0 \ CONFIG.C_M00_AXIS_IS_ACLK_ASYNC 0 \
CONFIG.C_M00_AXIS_REG_CONFIG 0 \ CONFIG.C_M00_AXIS_REG_CONFIG 0 \
CONFIG.C_S00_AXIS_IS_ACLK_ASYNC 0 \ CONFIG.C_S00_AXIS_IS_ACLK_ASYNC 0 \
CONFIG.C_S00_AXIS_REG_CONFIG 1 \ CONFIG.C_S00_AXIS_REG_CONFIG 0 \
CONFIG.C_S01_AXIS_IS_ACLK_ASYNC 0 \ CONFIG.C_S01_AXIS_IS_ACLK_ASYNC 0 \
CONFIG.C_S01_AXIS_REG_CONFIG 1 \ CONFIG.C_S01_AXIS_REG_CONFIG 0 \
CONFIG.C_SWITCH_MAX_XFERS_PER_ARB 1 \ CONFIG.C_SWITCH_MAX_XFERS_PER_ARB 1024 \
CONFIG.C_SWITCH_MI_REG_CONFIG 0 \ CONFIG.C_SWITCH_MI_REG_CONFIG 0 \
CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT 0 \ CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT 1 \
CONFIG.C_SWITCH_SI_REG_CONFIG 1 \ CONFIG.C_SWITCH_SI_REG_CONFIG 1 \
CONFIG.HAS_TDATA true \ CONFIG.HAS_TDATA true \
CONFIG.HAS_TDEST false \ CONFIG.HAS_TDEST false \
...@@ -21,27 +21,27 @@ set_property -dict [list \ ...@@ -21,27 +21,27 @@ set_property -dict [list \
CONFIG.HAS_TKEEP true \ CONFIG.HAS_TKEEP true \
CONFIG.HAS_TLAST true \ CONFIG.HAS_TLAST true \
CONFIG.HAS_TSTRB false \ CONFIG.HAS_TSTRB false \
CONFIG.HAS_TUSER false \ CONFIG.HAS_TUSER true \
CONFIG.M00_AXIS_FIFO_MODE {0_(Disabled)} \ CONFIG.M00_AXIS_FIFO_MODE {2_(Packet)} \
CONFIG.C_M00_AXIS_FIFO_DEPTH {2048} \
CONFIG.M00_AXIS_TDATA_NUM_BYTES 8 \ CONFIG.M00_AXIS_TDATA_NUM_BYTES 8 \
CONFIG.M00_S00_CONNECTIVITY true \ CONFIG.M00_S00_CONNECTIVITY true \
CONFIG.M00_S01_CONNECTIVITY true \ CONFIG.M00_S01_CONNECTIVITY true \
CONFIG.S00_AXIS_FIFO_MODE {0_(Disabled)} \ CONFIG.S00_AXIS_FIFO_MODE {0_(Disabled)} \
CONFIG.S00_AXIS_TDATA_NUM_BYTES 22 \ CONFIG.S00_AXIS_TDATA_NUM_BYTES 22 \
CONFIG.S01_AXIS_FIFO_MODE {0_(Disabled)} \ CONFIG.S01_AXIS_FIFO_MODE {0_(Disabled)} \
CONFIG.S01_AXIS_TDATA_NUM_BYTES 10 \ CONFIG.S01_AXIS_TDATA_NUM_BYTES 2 \
CONFIG.SWITCH_PACKET_MODE false \ CONFIG.SWITCH_PACKET_MODE false \
CONFIG.SWITCH_TDATA_NUM_BYTES 2 \ CONFIG.SWITCH_TDATA_NUM_BYTES 2 \
CONFIG.SWITCH_USE_ACLKEN false \ CONFIG.SWITCH_USE_ACLKEN false \
CONFIG.SYNCHRONIZATION_STAGES 2 \ CONFIG.SYNCHRONIZATION_STAGES 2 \
] [get_ips comcellnode_interco] ] [get_ips axis_interco_16]
# Unused properties # Unused properties
#CONFIG.C_S00_AXIS_ACLK_RATIO 12 \ #CONFIG.C_S00_AXIS_ACLK_RATIO 12 \
#CONFIG.C_S00_AXIS_FIFO_DEPTH 32 \ #CONFIG.C_S00_AXIS_FIFO_DEPTH 32 \
#CONFIG.C_S01_AXIS_ACLK_RATIO 12 \ #CONFIG.C_S01_AXIS_ACLK_RATIO 12 \
#CONFIG.C_S01_AXIS_FIFO_DEPTH 32 \ #CONFIG.C_S01_AXIS_FIFO_DEPTH 32 \
#CONFIG.C_M00_AXIS_FIFO_DEPTH 32 \
#CONFIG.C_M00_AXIS_ACLK_RATIO 12 \ #CONFIG.C_M00_AXIS_ACLK_RATIO 12 \
#CONFIG.C_M00_AXIS_BASETDEST 0x00000000 \ #CONFIG.C_M00_AXIS_BASETDEST 0x00000000 \
#CONFIG.C_M00_AXIS_HIGHTDEST 0x00000000 \ #CONFIG.C_M00_AXIS_HIGHTDEST 0x00000000 \
...@@ -80,3 +80,19 @@ set_property -dict [list \ ...@@ -80,3 +80,19 @@ set_property -dict [list \
] [get_ips axis_wconv_80_16] ] [get_ips axis_wconv_80_16]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath] set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
set xcipath [create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name axis_pkt_fifo_64]
set_property -dict [list \
CONFIG.TDATA_NUM_BYTES {8} \
CONFIG.TUSER_WIDTH {1} \
CONFIG.FIFO_DEPTH {256} \
CONFIG.FIFO_MODE {2} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.HAS_TKEEP {1} \
CONFIG.HAS_TLAST {1} \
CONFIG.HAS_PROG_EMPTY {0} \
] [get_ips axis_pkt_fifo_64]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
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