Add FWK TCL and RDL files

* Not tested

rdl/comcellnode.rdl

+`include "comcellnode.vh" // Auto generated by FWK
+
+
+addrmap COMCELLNODE {
+
+    desyrdl_generate_hdl = true;
+    desyrdl_interface = "AXI4L";
+
+    xil_ethsubsyst ETH @0x1000;
+
+    reg {
+
+    } CONTROL;
+
+    // MAC address
+    reg {
+        field {hw=r; sw=rw;} MAC[32];
+    } MAC_DST_LSB;
+
+    reg {
+        field {hw=r; sw=rw;} MAC[16];
+    } MAC_DST_MSB;
+
+    reg {
+        field {hw=r; sw=rw;} MAC[32];
+    } MAC_SRC_LSB;
+
+    reg {
+        field {hw=r; sw=rw;} MAC[16];
+    } MAC_SRC_MSB;
+
+    reg {
+        field {hw=r; sw=rw;} LENGTH[16];
+    } MAC_LENGTH;
+
+    reg {
+        field {hw=r; sw=rw;} TIMEOUT[16];
+        field {hw=r; sw=rw;} COUNT[8];
+        field {hw=r; sw=rw;} RUN;
+    } PACKETER_BPM_FRAME;
+
+    reg {
+        field {hw=w; sw=r;} COUNT[32];
+    } PACKETER_COUNT;
+
+    reg {
+        field {hw=w; sw=r; rclkr; sticky;} SEQUENCE;
+        field {hw=w; sw=r; rclkr; sticky;} TIMEOUT;
+    } PACKETER_ERROR;
+
+    reg {
+        field {hw=r; sw=rw;} RST_TX_CLK;
+        field {hw=r; sw=rw;} RST_RX_CLK;
+        field {hw=r; sw=rw;} RST_TX_DATA;
+        field {hw=r; sw=rw;} RST_RX_DATA;
+        field {hw=r; sw=rw;} RST_TX;
+        field {hw=r; sw=rw;} RST_RX;
+        field {hw=r; sw=rw;} LOOPBACK[3];
+    } ETH_GT_CONTROL;
+
+    reg {
+        field {hw=w; sw=r;} CDR_STABLE;
+        field {hw=w; sw=r;} SFP_RX_LOS;
+        field {hw=w; sw=r;} SFP_MOD_ABS;
+        field {hw=w; sw=r;} SFP_TX_FAULT;
+    } ETH_GT_STATUS;
+
+};

tcl/main.tcl

+################################################################################
+# Main tcl for the module
+################################################################################
+
+# ==============================================================================
+proc init {} {
+
+    # Configuration
+
+}
+
+# ==============================================================================
+proc setSources {} {
+  variable Vhdl
+  variable Verilog
+
+  # Generate VHDL package with modle version
+  genModVerFile VHDL ../hdl/pkg_version.vhd
+
+  lappend Vhdl ../hdl/pkg_bpmframe_stream.vhd
+  lappend Vhdl ../hdl/comcellnode_ethernet.vhd
+  lappend Vhdl ../hdl/comcellnode_packeter.vhd
+  lappend Vhdl ../hdl/top_comcellnode.vhd
+
+  lappend Verilog ../hdl/comcellnode_ethernet_reset_wrapper.v
+
+}
+
+# ==============================================================================
+proc setAddressSpace {} {
+    variable AddressSpace
+    addAddressSpace AddressSpace "COMCELLNODE" RDL {} ../rdl/comcellnode.rdl
+    addAddressSpace AddressSpace "xil_ethsubsyst" RDL {} ../rdl/xil_ethsubsyst.rdl
+}
+
+# ==============================================================================
+proc doOnCreate {} {
+  variable Vhdl
+  variable Verilog
+  addSources Vhdl
+  addSources Verilog
+
+  # TODO sould probably get that part number from the project configuration
+  set fpga_part "xczu11eg-ffvc1760-2L-e"
+  set_property part ${fpga_part} [current_project]
+  set_property target_language VHDL [current_project]
+
+  # Create GT wizard IP
+  source ../tcl/combpm_gtwizard.tcl
+}
+
+# ==============================================================================
+proc doOnBuild {} {
+}
+
+# ==============================================================================
+proc setSim {} {
+}