Initial commit

Makefile

+###############################################################################
+# Global receipes
+none:
+	$(info You should specify what to make: ip, sim, clean, clean-all)
+
+sim:
+
+###############################################################################
+# Configuration
+hdlpkgsrc := 
+
+###############################################################################
+# Generate a source list, depending on the config
+rdlsrc := $(shell ls rdl/*.rdl)
+rdltarget := $(rdlsrc:rdl/%.rdl=hdl/%.vhd)
+hdlsrc := $(shell ls hdl/*.vhd) $(rdltarget) $(hdlpkgsrc)
+# TODO: depends on the configuration
+tcl/sources.tcl:
+	echo read_vhdl {$(hdlsrc)} > $@
+
+###############################################################################
+# Compute interface from rdl files
+hdl/%.vhd:rdl/%.rdl
+	hectare --axi-vhdl $@ $<
+
+###############################################################################
+# Package IP
+ip:component.xml
+
+component.xml:tcl/sources.tcl tcl/comcellnode.tcl tcl/generate_ethernet.tcl $(hdlsrc)
+	vivado -mode batch -source tcl/comcellnode.tcl
+
+###############################################################################
+# Synthessize IP for test
+synth:component.xml
+	vivado -mode batch -source tcl/bloc_synthesis.tcl
+
+
+
+
+###############################################################################
+# Cleaner Rules
+clean:
+	rm -f vivado*.log vivado*.jou
+
+clean-ip:
+	rm -rf ip_proj ip_user_files xgui
+	rm -f component.xml
+
+clean-sim:
+	rm -f *.wdb
+
+clean-all:clean-ip clean
+	rm -f tcl/sources.tcl
+
+.PHONY: clean clean-ip clean-sim clean-all none ip sim synth

tcl/comcellnode.tcl

+# Source metadata
+set design "comcellnode"
+set top top_comcellnode
+set part "xczu11eg-ffvc1760-2L-e"
+
+# Create project
+set ip_project [create_project -name ${design} -part ${part} -in_memory ]
+set_property top ${top} [current_fileset]
+
+# Compilation order in auto
+set_property source_mgmt_mode All ${ip_project}
+
+# Read sources
+source tcl/sources.tcl
+
+# Generate Xilinx IP
+source tcl/generate_ethernet.tcl
+
+# Compile order to auto
+update_compile_order -fileset sources_1
+
+# Package project
+set ip_properties [ list \
+    vendor "synchrotron-soleil.fr" \
+    library "user" \
+    name ${design} \
+    version "1.0" \
+    taxonomy "/Communication_&_Networking/Serial_Interfaces" \
+    display_name "Cell node Communication" \
+    description "Embed ethernet IP to perform inter cellnode communication." \
+    vendor_display_name "Synchrotron SOLEIL" \
+    company_url "http://www.synchrotron-soleil.fr" \
+    ]
+
+set family_lifecycle [list \
+  zynquplus{${part}} Beta \
+]
+
+ipx::package_project
+set ip_core [ipx::current_core]
+set_property -dict ${ip_properties} ${ip_core}
+set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
+
+# Associate AX/AXIS interfaces and reset with clock
+# Done in VHDL file
+
+# Remove default address map
+ipx::remove_memory_map [lindex [split [ipx::get_memory_maps]] 2] [ipx::current_core]
+
+# Create Address map
+set s_axi_mm [ipx::add_memory_map s_axi_ctrl [ipx::current_core]]
+set_property slave_memory_map_ref s_axi_ctrl [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
+set_property ENABLEMENT_PRESENCE required ${s_axi_mm}
+
+set s_axi_blk [ipx::add_address_block registers ${s_axi_mm}]
+set_property -dict { \
+	ACCESS "read-write" \
+	DESCRIPTION "Control and status registers" \
+	ENABLEMENT_PRESENCE required \
+	NAME "registers" \
+	RANGE 256 \
+	USAGE "register" \
+	WIDTH 8 \
+	} ${s_axi_blk}
+
+ # Save IP and close project
+ipx::check_integrity ${ip_core}
+ipx::save_core ${ip_core}
+close_project

tcl/generate_ethernet.tcl

+set gth_loc "X0Y5"
+
+set xcipath [create_ip -name xxv_ethernet -vendor xilinx.com -library ip -version 3.3 -module_name comcellnode_ethernet]
+
+set_property -dict [list \
+    CONFIG.CORE {Ethernet MAC+PCS/PMA 64-bit} \
+    CONFIG.LINE_RATE {10} \
+    CONFIG.DATA_PATH_INTERFACE {AXI Stream} \
+    CONFIG.BASE_R_KR {BASE-R} \
+    CONFIG.INCLUDE_AXI4_INTERFACE {1} \
+    CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \
+    CONFIG.INCLUDE_USER_FIFO {1} \
+    CONFIG.ENABLE_TX_FLOW_CONTROL_LOGIC {0} \
+    CONFIG.ENABLE_DATAPATH_PARITY {0} \
+    CONFIG.GT_LOCATION {0} \
+    CONFIG.GT_REF_CLK_FREQ {156.25} \
+    CONFIG.GT_TYPE {GTH} \
+    CONFIG.LANE1_GT_LOC $gth_loc \
+    CONFIG.ENABLE_PIPELINE_REG {1} \
+    CONFIG.ADD_GT_CNTRL_STS_PORTS {1} \
+    CONFIG.INCLUDE_SHARED_LOGIC {0} \
+    ] [get_ips comcellnode_ethernet]
+
+set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
+
+
+set xcipath [create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name comcellnode_gtwizard]
+
+set_property -dict [list \
+    CONFIG.preset {GTH-10GBASE-R} \
+    ] [get_ips comcellnode_gtwizard]
+
+set_property -dict [list \
+    CONFIG.CHANNEL_ENABLE $gth_loc \
+    CONFIG.TX_MASTER_CHANNEL $gth_loc \
+    CONFIG.RX_MASTER_CHANNEL $gth_loc \
+    CONFIG.RX_REFCLK_SOURCE "$gth_loc clk1" \
+    CONFIG.TX_REFCLK_SOURCE "$gth_loc clk1" \
+    CONFIG.FREERUN_FREQUENCY {100} \
+    CONFIG.LOCATE_COMMON {EXAMPLE_DESIGN} \
+    CONFIG.LOCATE_TX_USER_CLOCKING {CORE} \
+    CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \
+    CONFIG.LOCATE_RESET_CONTROLLER {CORE} \
+    CONFIG.LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN} \
+    CONFIG.ENABLE_OPTIONAL_PORTS {loopback_in} \
+    ] [get_ips comcellnode_gtwizard]
+
+set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]