WIP Add BPM packeter

* Only Sequence detector and frame counter
* No header insertion yet
* Not simulated, not synthesized

hdl/comcellnode_packeter.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.pkg_bpmframe_stream.all;
+
+
+entity comcellnode_packeter is
+    port(
+        aclk                                : in std_logic;
+        aresetn                             : in std_logic;
+
+        -- Slave interface (BPM com input)
+        s_axis_tid                          : in std_logic_vector(0 downto 0);
+        s_axis_tdest                        : in std_logic_vector(9 downto 0);
+        s_axis_tdata                        : in std_logic_vector(127 downto 0);
+        s_axis_tstrb                        : in std_logic_vector(15 downto 0);
+        s_axis_tkeep                        : in std_logic_vector(15 downto 0);
+        s_axis_tlast                        : in std_logic;
+        s_axis_tuser                        : in std_logic_vector(0 downto 0);
+        s_axis_tvalid                       : in std_logic;
+        s_axis_tready                       : out std_logic;
+
+        -- master interface (packet output)
+        m_axis_tvalid                       : out std_logic;
+        m_axis_tready                       : in std_logic;
+        m_axis_tdata                        : out std_logic_vector(63 downto 0);
+        m_axis_tkeep                        : out std_logic_vector(7 downto 0);
+        m_axis_tlast                        : out std_logic;
+        m_axis_tuser                        : out std_logic;
+
+        -- Control
+        packeter_run                        : in std_logic;
+
+        -- Configuration
+        mac_dst                             : in std_logic_vector(47 downto 0);
+        mac_src                             : in std_logic_vector(47 downto 0);
+        mac_length                          : in std_logic_vector(15 downto 0);
+
+        bpm_frame_cnt                       : in std_logic_vector(7 downto 0);
+        timeref                             : in std_logic_vector(63 downto 0)
+        );
+end entity comcellnode_packeter;
+
+
+architecture rtl of comcellnode_packeter is
+
+    ----------------------
+    -- TYPE DECLARATION --
+    ----------------------
+    type t_state is (STANDBY, RUN, ERR_TO, ERR_SEQ);
+
+    ------------------------
+    -- SIGNAL DECLARATION --
+    ------------------------
+    signal bpm_reg_m_tvalid         : std_logic;
+    signal bpm_reg_m_tready         : std_logic;
+    signal bpm_reg_m_tdata          : std_logic_vector(C_W_BPMFRAME_TDATA-1 downto 0);
+    signal bpm_reg_bpmframe         : t_bpmframe;
+
+    signal prev_seq_r               : std_logic_vector(C_W_BPMFRAME_FASEQ-1 downto 0);
+    signal new_seq_valid_r          : std_logic;
+    signal new_seq                  : std_logic;
+
+    signal reg_tvalid               : std_logic;
+
+    signal frame_cnt                : unsigned(7 downto 0);
+    signal frame_cnt_decr           : std_logic;
+    signal frame_cnt_zero           : std_logic;
+
+    signal bpm_wconv_s_tvalid       : std_logic;
+    signal bpm_wconv_s_tready       : std_logic;
+    signal bpm_wconv_s_tlast        : std_logic;
+    signal bpm_wconv_s_tdata        : std_logic_vector(79 downto 0);
+    signal bpm_wconv_s_tuser        : std_logic_vector(9 downto 0);
+    signal bpm_wconv_m_tvalid       : std_logic;
+    signal bpm_wconv_m_tready       : std_logic;
+    signal bpm_wconv_m_tlast        : std_logic;
+    signal bpm_wconv_m_tdata        : std_logic_vector(15 downto 0);
+    signal bpm_wconv_m_tuser        : std_logic_vector(1 downto 0);
+
+    signal fsm_state                : t_state;
+    signal fsm_state_next           : t_state;
+    signal dump                     : std_logic;
+    signal pass                     : std_logic;
+    signal frame_error              : std_logic;
+    signal load_frame_cnt_ena       : std_logic;
+    signal frame_timeout            : std_logic;
+
+
+begin
+
+    ------------------------
+    -- BPM INPUT REGISTER --
+    ------------------------
+    inst_regslice : entity work.axis_reg_128
+    port map (
+        aclk => aclk,
+        aresetn => aresetn,
+        s_axis_tvalid => s_axis_tvalid,
+        s_axis_tready => s_axis_tready,
+        s_axis_tdata => s_axis_tdata,
+        m_axis_tvalid => bpm_reg_m_tvalid,
+        m_axis_tready => bpm_reg_m_tready,
+        m_axis_tdata => bpm_reg_m_tdata
+    );
+    bpm_reg_bpmframe <= slv2bpmframe(bpm_reg_m_tdata);
+
+    -- Seq FA sequence detector
+    new_seq         <= (new_seq_valid_r and bpm_reg_m_tvalid) when bpm_reg_bpmframe.fa_seq = prev_seq_r else '0';
+
+    p_seq_detect:process(aclk, aresetn)
+    begin
+        if aresetn = '0' then
+            prev_seq_r          <= (others => '0');
+            new_seq_valid_r     <= '0';
+        elsif rising_edge(aclk) then
+            if (bpm_reg_m_tvalid and bpm_reg_m_tready) = '1' then
+                prev_seq_r      <= bpm_reg_bpmframe.fa_seq;
+                new_seq_valid_r <= '1';
+            end if;
+        end if;
+    end process;
+
+    ----------------------------
+    -- DUMP/PASS AXIS CIRCUIT --
+    ----------------------------
+    bpm_reg_m_tready    <= dump or (pass and bpm_wconv_s_tready);
+    reg_tvalid          <= pass and bpm_reg_m_tvalid;
+
+
+    ------------------------
+    -- BPM PACKET COUNTER --
+    ------------------------
+    frame_cnt_decr      <= reg_tvalid and bpm_reg_m_tready;
+    frame_cnt_zero      <= '1' when frame_cnt = 0 else '0';
+
+    p_frame_cnt:process(aclk, aresetn)
+    begin
+        if aresetn = '0' then
+            frame_cnt   <= (others => '0');
+
+        elsif rising_edge(aclk) then
+            if load_frame_cnt_ena = '1' then
+                frame_cnt <= unsigned(bpm_frame_cnt);
+            else
+                if frame_cnt_decr = '1' then
+                    frame_cnt <= frame_cnt -1;
+                end if;
+            end if;
+        end if;
+    end process p_frame_cnt;
+
+    --------------------------
+    -- AXIS WIDTH CONVERTER --
+    --------------------------
+    bpm_wconv_s_tdata       <= bpm_reg_bpmframe.bpm_id & bpm_reg_bpmframe.pos_x & bpm_reg_bpmframe.pos_y;
+    bpm_wconv_s_tvalid      <= frame_error or reg_tvalid;
+    bpm_wconv_s_tlast       <= frame_error or frame_cnt_zero;
+    bpm_wconv_s_tuser       <= (others => frame_error);
+
+    -- temporary
+    bpm_wconv_m_tready  <= m_axis_tready;
+
+
+    inst_wconv: entity work.axis_wconv_80_16
+    port map(
+        aclk                => aclk,
+        aresetn             => aresetn,
+        s_axis_tvalid       => bpm_wconv_s_tvalid,
+        s_axis_tready       => bpm_wconv_s_tready,
+        s_axis_tdata        => bpm_wconv_s_tdata,
+        s_axis_tlast        => bpm_wconv_s_tlast,
+        s_axis_tuser        => bpm_wconv_s_tuser,
+        m_axis_tvalid       => bpm_wconv_m_tvalid,
+        m_axis_tready       => bpm_wconv_m_tready,
+        m_axis_tdata        => bpm_wconv_m_tdata,
+        m_axis_tuser        => bpm_wconv_m_tuser,
+        m_axis_tlast        => bpm_wconv_m_tlast
+    );
+
+
+    ---------
+    -- FSM --
+    ---------
+
+    -- temporary
+    frame_timeout <= '0';
+
+    p_fsm_sync:process(aclk, aresetn)
+    begin
+        if aresetn = '0' then
+            fsm_state   <= STANDBY;
+        elsif rising_edge(aclk) then
+            fsm_state   <= fsm_state_next;
+        end if;
+    end process p_fsm_sync;
+
+    p_fsm_comb:process(packeter_run, new_seq, frame_cnt_zero, bpm_wconv_s_tready, frame_timeout)
+    begin
+        case fsm_state is
+            when STANDBY =>
+                dump                    <= '1';
+                load_frame_cnt_ena      <= '1';
+                pass                    <= '0';
+                frame_error             <= '0';
+                --
+                if (packeter_run and new_seq) = '1' then
+                    fsm_state_next <= RUN;
+                end if;
+
+            when RUN =>
+                dump                    <= '0';
+                load_frame_cnt_ena      <= '0';
+                pass                    <= '1';
+                frame_error             <= '0';
+                --
+                if new_seq  = '1' then
+                    fsm_state_next <= ERR_SEQ;
+                elsif frame_timeout = '1' then
+                    fsm_state_next <= ERR_TO;
+                elsif frame_cnt_zero = '0' then
+                    fsm_state_next <= STANDBY;
+                end if;
+
+            when ERR_TO =>
+                dump                    <= '1';
+                load_frame_cnt_ena      <= '0';
+                pass                    <= '0';
+                frame_error             <= '1';
+                --
+                if bpm_wconv_s_tready = '1' then
+                    fsm_state_next <= STANDBY;
+                end if;
+
+            when ERR_SEQ =>
+                dump                    <= '1';
+                load_frame_cnt_ena      <= '0';
+                pass                    <= '0';
+                frame_error             <= '1';
+                --
+                if bpm_wconv_s_tready = '1' then
+                    fsm_state_next <= STANDBY;
+                end if;
+
+            when others =>
+                dump                    <= '1';
+                load_frame_cnt_ena      <= '1';
+                pass                    <= '0';
+                frame_error             <= '0';
+                --
+                fsm_state_next <= STANDBY;
+
+        end case;
+    end process p_fsm_comb;
+
+
+end architecture rtl;

hdl/pkg_bpmframe_stream.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+package pkg_bpmframe_stream is
+
+    ----------------------
+    -- MACRO PARAMETERS --
+    ----------------------
+    constant C_W_BPMFRAME_TDEST     : natural := 7;
+    constant C_W_BPMFRAME_TDATA     : natural := 128;
+
+    constant C_W_BPMFRAME_FASEQ     : natural := 8;
+    constant C_W_BPMFRAME_POS       : natural := 32;
+    constant C_W_BPMFRAME_TS        : natural := 40;
+    constant C_W_BPMFRAME_ID        : natural := 16;
+
+    ---------------------------------
+    -- AXIS MASTER/SLAVE INTERFACE --
+    ---------------------------------
+    type t_bpmframe_axis_m2s is record
+        tdest  : std_logic_vector(C_W_BPMFRAME_TDEST-1 downto 0);
+        tdata  : std_logic_vector(C_W_BPMFRAME_TDATA-1 downto 0);
+        tlast  : std_logic;
+        tvalid : std_logic;
+        ---tid    : std_logic_vector(0 downto 0);
+        --tuser  : std_logic_vector(0 downto 0);
+        --tstrb  : std_logic_vector(15 downto 0);
+        --tkeep  : std_logic_vector(15 downto 0);
+    end record t_bpmframe_axis_m2s;
+
+    type t_bpmframe_axis_s2m is record
+        tready : std_logic;
+    end record t_bpmframe_axis_s2m;
+
+    subtype t_bpmframe_m_axis_out is t_bpmframe_axis_m2s;
+    subtype t_bpmframe_s_axis_in  is t_bpmframe_axis_m2s;
+    subtype t_bpmframe_m_axis_in  is t_bpmframe_axis_s2m;
+    subtype t_bpmframe_s_axis_out is t_bpmframe_axis_s2m;
+
+    ------------------------
+    -- AXIS STREAM PACKET --
+    ------------------------
+    type t_bpmframe is record
+        pos_x                        : std_logic_vector(C_W_BPMFRAME_POS-1 downto 0);
+        pos_y                        : std_logic_vector(C_W_BPMFRAME_POS-1 downto 0);
+        bpm_id                       : std_logic_vector(C_W_BPMFRAME_ID-1 downto 0);
+        mc_timestamp                 : std_logic_vector(C_W_BPMFRAME_TS-1 downto 0);
+        fa_seq                       : std_logic_vector(C_W_BPMFRAME_FASEQ-1 downto 0);
+    end record t_bpmframe;
+
+    constant C_BPMFRAME_ZERO : t_bpmframe := (
+        pos_x         => (others => '0'),
+        pos_y         => (others => '0'),
+        bpm_id        => (others => '0'),
+        mc_timestamp  => (others => '0'),
+        fa_seq        => (others => '0')
+        );
+
+    function slv2bpmframe(
+        signal tdata : std_logic_vector(C_W_BPMFRAME_TDATA-1 downto 0)
+        )
+        return t_bpmframe;
+
+    function bpmframe2slv(
+        signal packet : t_bpmframe
+        )
+        return std_logic_vector;
+
+
+end package;
+
+package body pkg_bpmframe_stream is
+
+
+    function slv2bpmframe(
+        signal tdata : std_logic_vector(C_W_BPMFRAME_TDATA-1 downto 0)
+        )
+        return t_bpmframe is
+        variable packet : t_bpmframe;
+    begin
+        packet.pos_x        := tdata(31 downto 0);
+        packet.pos_y        := tdata(63 downto 32);
+        packet.bpm_id       := tdata(79 downto 64);
+        packet.mc_timestamp := tdata(119 downto 80);
+        packet.fa_seq       := tdata(127 downto 120);
+        return packet;
+    end function;
+
+    function bpmframe2slv(
+        signal packet : t_bpmframe
+        )
+        return std_logic_vector is
+    begin
+        return packet.fa_seq & packet.mc_timestamp & packet.bpm_id & packet.pos_y & packet.pos_x;
+    end function;
+
+end package body;

sim/simulate.tcl

+exec rm -rf simproj
+create_project sim_packeter simproj
+
+set_property source_mgmt_mode All [current_project]
+
+read_vhdl {hdl/comcellnode_packeter.vhd sim/tb_comcellnode_packeter.vhd}
+read_vhdl {hdl/pkg_bpmframe_stream.vhd}
+source tcl/generate_axisinterco.tcl
+
+update_compile_order -fileset sim_1
+launch_simulation
+close_wave_config
+open_wave_config sim/tb_comcellnode_packeter.wcfg
+restart
+run 10 us
+

sim/tb_comcellnode_packeter.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.uniform;
+use ieee.math_real.ceil;
+
+entity tb_comcellnode_packeter is
+end entity;
+
+architecture testbench of tb_comcellnode_packeter is
+
+    --------------------------
+    -- CONSTANT DECLARATION --
+    --------------------------
+    constant RX_COOLDOWN    : positive = 3;
+
+    ------------------------
+    -- SIGNAL DECLARATION --
+    ------------------------
+    signal tb_clk       : std_logic := '0';
+    signal tb_rstn      : std_logic := '1';
+
+    signal tb_s_axis_tid           : std_logic_vector(0 downto 0);
+    signal tb_s_axis_tdest         : std_logic_vector(9 downto 0);
+    signal tb_s_axis_tdata         : std_logic_vector(127 downto 0);
+    signal tb_s_axis_tstrb         : std_logic_vector(15 downto 0);
+    signal tb_s_axis_tkeep         : std_logic_vector(15 downto 0);
+    signal tb_s_axis_tlast         : std_logic;
+    signal tb_s_axis_tuser         : std_logic_vector(0 downto 0);
+    signal tb_s_axis_tvalid        : std_logic;
+    signal tb_s_axis_tready        : std_logic;
+    signal tb_m_axis_tvalid   : std_logic;
+    signal tb_m_axis_tready   : std_logic;
+    signal tb_m_axis_tdata    : std_logic_vector(63 downto 0);
+    signal tb_m_axis_tkeep    : std_logic_vector(7 downto 0);
+    signal tb_m_axis_tlast    : std_logic;
+    signal tb_m_axis_tuser    : std_logic;
+    signal tb_timeref              : unsigned(63 downto 0);
+    signal tb_bpm_frame_cnt : std_logic_vector(7 downto 0);
+    signal tb_packeter_run : std_logic;
+    signal tb_mac_dst     : std_logic_vector(47 downto 0);
+    signal tb_mac_src     : std_logic_vector(47 downto 0);
+    signal tb_mac_length  : std_logic_vector(15 downto 0);
+
+    signal tx_send      : boolean := false;
+    signal rx_recv      : boolean := false;
+
+
+begin
+
+    -- clock generation
+    tb_clk <= not tb_clk after 10 ns;
+
+    -----------------------
+    -- DUT INSTANCIATION --
+    -----------------------
+    inst_dut: entity work.comcellnode_packeter
+    port map(
+        aclk            => tb_clk,
+        aresetn         => tb_rstn,
+
+        -- Slave interface (BPM com input)
+        s_axis_tid           => tb_s_axis_tid,
+        s_axis_tdest         => tb_s_axis_tdest,
+        s_axis_tdata         => tb_s_axis_tdata,
+        s_axis_tstrb         => tb_s_axis_tstrb,
+        s_axis_tkeep         => tb_s_axis_tkeep,
+        s_axis_tlast         => tb_s_axis_tlast,
+        s_axis_tuser         => tb_s_axis_tuser,
+        s_axis_tvalid        => tb_s_axis_tvalid,
+        s_axis_tready        => tb_s_axis_tready,
+
+        -- master interface (packet output)
+        m_axis_tvalid   => tb_m_axis_tvalid,
+        m_axis_tready   => tb_m_axis_tready,
+        m_axis_tdata    => tb_m_axis_tdata,
+        m_axis_tkeep    => tb_m_axis_tkeep,
+        m_axis_tlast    => tb_m_axis_tlast,
+        m_axis_tuser    => tb_m_axis_tuser,
+
+        packeter_run    => tb_packeter_run,
+
+        mac_dst     => tb_mac_dst,
+        mac_src     => tb_mac_src,
+        mac_length  => tb_mac_length,
+
+        bpm_frame_cnt => tb_bpm_frame_cnt,
+        timeref              => std_logic_vector(tb_timeref)
+    );
+
+    -- Timeref counter
+    p_timeref: process(tb_clk, tb_rstn)
+    begin
+        if tb_rstn = '0' then
+            tb_timeref <= (others => '0');
+        elsif rising_edge(tb_clk) then
+            tb_timeref <= tb_timeref+1;
+        end if;
+    end process p_timeref;
+
+    ------------------
+    -- MAIN PROCESS --
+    ------------------
+    p_main: process
+        variable randint : positive;
+        variable x : real;
+        variable seed1 : positive := 1;
+        variable seed2 : positive := 2;
+    begin
+
+        -- let it running then reset, synchronous deassertion
+        wait for 77 ns;
+        tb_rstn <= '0';
+        wait until rising_edge(tb_clk);
+        tb_mac_dst      <= (others => '0');
+        tb_mac_src      <= (others => '0');
+        tb_mac_length   <= (others => '0');
+        tb_packeter_run <= '1';
+        wait for 40 ns;
+        wait until rising_edge(tb_clk);
+        tb_rstn <= '1';
+        wait until rising_edge(tb_clk);
+
+        for I in 0 to 20 loop
+            wait until rising_edge(tb_clk);
+        end loop;
+
+        -- Configuration values
+        tb_mac_dst <= x"010000DBAAFF";
+        tb_mac_src <= x"050000DBAAFF";
+        tb_bpm_frame_cnt <= x"05";
+        tb_mac_length  <= x"003A"; -- 58 Bytes: 5 BPM frames
+        wait until rising_edge(tb_clk);
+
+        -- Send some BPM frames
+        tx_send <= true;
+
+        -- Never ending end
+        wait;
+
+    end process p_main;
+
+
+    ---------------
+    -- TX STREAM --
+    ---------------
+    p_tx_send:process
+        -- RANDOM GENERATOR --
+        variable seed1, seed2   : integer       := 666;
+        impure function rand_slv(len : integer) return std_logic_vector is
+            variable r                  : real;
+            variable slv                : std_logic_vector(len - 1 downto 0);
+        begin
+            for i in slv'range loop
+                uniform(seed1, seed2, r);
+                if r > 0.5  then
+                    slv(i) := '1';
+                else
+                    slv(i) := '0';
+                end if;
+            end loop;
+            return slv;
+        end function;
+
+    begin
+        s_axis_tvalid   <= '0';
+
+        while true loop
+            if not tx_send then
+                wait until tx_send;
+                wait until rising_edge(clk);
+            end if;
+            s_axis_tdata    <= rand_slv(128);
+            s_axis_tvalid   <= '1';
+            if tx_last then
+                s_axis_tlast    <= '1';
+            else
+                s_axis_tlast    <= '0';
+            end if;
+            wait until rising_edge(clk) and s_axis_tready='1';
+            s_axis_tvalid   <= '0';
+        end loop;
+
+    end process p_tx_send;
+
+    ---------------
+    -- RX STREAM --
+    ---------------
+    p_rx_recv:process
+    begin
+        while true loop
+            if not rx_recv then
+                m_axis_tready   <= '0';
+                wait until rx_recv and rising_edge(clk);
+            end if;
+            m_axis_tready   <= '1';
+            wait until rising_edge(clk) and m_axis_tvalid ='1';
+            m_axis_tready   <= '0';
+            for I in 0 to RX_COOLDOWN loop
+                wait until rising_edge(clk);
+            end loop;
+        end loop;
+    end process p_rx_recv;
+
+
+end architecture testbench;
+

sim/tb_comcellnode_packeter.wcfg

+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_comcellnode_packeter_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="pkg_bpmframe_stream" />
+            <top_module name="tb_comcellnode_packeter" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="1321185fs"></ZoomEndTime>
+      <Cursor1Time time="10000000fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="224"></NameColumnWidth>
+      <ValueColumnWidth column_width="134"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="29" />
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_clk">
+      <obj_property name="ElementShortName">tb_clk</obj_property>
+      <obj_property name="ObjectShortName">tb_clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_rstn">
+      <obj_property name="ElementShortName">tb_rstn</obj_property>
+      <obj_property name="ObjectShortName">tb_rstn</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/tb_timeref">
+      <obj_property name="ElementShortName">tb_timeref[63:0]</obj_property>
+      <obj_property name="ObjectShortName">tb_timeref[63:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider91" type="divider">
+      <obj_property name="label">AXIS BPM input</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/tb_s_axis_tdata">
+      <obj_property name="ElementShortName">tb_s_axis_tdata[127:0]</obj_property>
+      <obj_property name="ObjectShortName">tb_s_axis_tdata[127:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_s_axis_tvalid">
+      <obj_property name="ElementShortName">tb_s_axis_tvalid</obj_property>
+      <obj_property name="ObjectShortName">tb_s_axis_tvalid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/tb_s_axis_tready">
+      <obj_property name="ElementShortName">tb_s_axis_tready</obj_property>
+      <obj_property name="ObjectShortName">tb_s_axis_tready</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider90" type="divider">
+      <obj_property name="label">AXIS S wconv</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tvalid">
+      <obj_property name="ElementShortName">bpm_wconv_s_tvalid</obj_property>
+      <obj_property name="ObjectShortName">bpm_wconv_s_tvalid</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tready">
+      <obj_property name="ElementShortName">bpm_wconv_s_tready</obj_property>
+      <obj_property name="ObjectShortName">bpm_wconv_s_tready</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tlast">
+      <obj_property name="ElementShortName">bpm_wconv_s_tlast</obj_property>
+      <obj_property name="ObjectShortName">bpm_wconv_s_tlast</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tdata">
+      <obj_property name="ElementShortName">bpm_wconv_s_tdata[79:0]</obj_property>
+      <obj_property name="ObjectShortName">bpm_wconv_s_tdata[79:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/bpm_wconv_s_tuser">
+      <obj_property name="ElementShortName">bpm_wconv_s_tuser[9:0]</obj_property>
+      <obj_property name="ObjectShortName">bpm_wconv_s_tuser[9:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider92" type="divider">
+      <obj_property name="label">Config</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/packeter_run">
+      <obj_property name="ElementShortName">packeter_run</obj_property>
+      <obj_property name="ObjectShortName">packeter_run</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/tb_mac_dst">
+      <obj_property name="ElementShortName">tb_mac_dst[47:0]</obj_property>
+      <obj_property name="ObjectShortName">tb_mac_dst[47:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/tb_mac_src">
+      <obj_property name="ElementShortName">tb_mac_src[47:0]</obj_property>
+      <obj_property name="ObjectShortName">tb_mac_src[47:0]</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/tb_mac_length">
+      <obj_property name="ElementShortName">tb_mac_length[15:0]</obj_property>
+      <obj_property name="ObjectShortName">tb_mac_length[15:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider85" type="divider">
+      <obj_property name="label">Interco</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider111" type="divider">
+      <obj_property name="label">FSM</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="other" fp_name="/tb_comcellnode_packeter/inst_dut/fsm_state">
+      <obj_property name="ElementShortName">fsm_state</obj_property>
+      <obj_property name="ObjectShortName">fsm_state</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/dump">
+      <obj_property name="ElementShortName">dump</obj_property>
+      <obj_property name="ObjectShortName">dump</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/pass">
+      <obj_property name="ElementShortName">pass</obj_property>
+      <obj_property name="ObjectShortName">pass</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/frame_error">
+      <obj_property name="ElementShortName">frame_error</obj_property>
+      <obj_property name="ObjectShortName">frame_error</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/load_frame_cnt_ena">
+      <obj_property name="ElementShortName">load_frame_cnt_ena</obj_property>
+      <obj_property name="ObjectShortName">load_frame_cnt_ena</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/frame_timeout">
+      <obj_property name="ElementShortName">frame_timeout</obj_property>
+      <obj_property name="ObjectShortName">frame_timeout</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider119" type="divider">
+      <obj_property name="label">Frame cnt, new seq</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_comcellnode_packeter/inst_dut/frame_cnt">
+      <obj_property name="ElementShortName">frame_cnt[7:0]</obj_property>
+      <obj_property name="ObjectShortName">frame_cnt[7:0]</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_comcellnode_packeter/inst_dut/new_seq">
+      <obj_property name="ElementShortName">new_seq</obj_property>
+      <obj_property name="ObjectShortName">new_seq</obj_property>
+   </wvobject>
+</wave_config>

tcl/generate_axisinterco.tcl

+# GENERATE AXI INTERCONNECT
+set xcipath [create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name comcellnode_interco]
+
+set_property -dict [list \
+        CONFIG.ARBITER_TYPE {Fixed} \
+        CONFIG.C_NUM_SI_SLOTS {2} \
+        CONFIG.C_NUM_MI_SLOTS {1} \
+        CONFIG.C_M00_AXIS_IS_ACLK_ASYNC 0 \
+        CONFIG.C_M00_AXIS_REG_CONFIG 0 \
+        CONFIG.C_S00_AXIS_IS_ACLK_ASYNC 0 \
+        CONFIG.C_S00_AXIS_REG_CONFIG 1 \
+        CONFIG.C_S01_AXIS_IS_ACLK_ASYNC 0 \
+        CONFIG.C_S01_AXIS_REG_CONFIG 1 \
+        CONFIG.C_SWITCH_MAX_XFERS_PER_ARB 1 \
+        CONFIG.C_SWITCH_MI_REG_CONFIG 0 \
+        CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT 0 \
+        CONFIG.C_SWITCH_SI_REG_CONFIG 1 \
+        CONFIG.HAS_TDATA true \
+        CONFIG.HAS_TDEST false \
+        CONFIG.HAS_TID false \
+        CONFIG.HAS_TKEEP true \
+        CONFIG.HAS_TLAST true \
+        CONFIG.HAS_TSTRB false \
+        CONFIG.HAS_TUSER false \
+        CONFIG.M00_AXIS_FIFO_MODE {0_(Disabled)} \
+        CONFIG.M00_AXIS_TDATA_NUM_BYTES 8 \
+        CONFIG.M00_S00_CONNECTIVITY true \
+        CONFIG.M00_S01_CONNECTIVITY true \
+        CONFIG.S00_AXIS_FIFO_MODE {0_(Disabled)} \
+        CONFIG.S00_AXIS_TDATA_NUM_BYTES 22  \
+        CONFIG.S01_AXIS_FIFO_MODE {0_(Disabled)} \
+        CONFIG.S01_AXIS_TDATA_NUM_BYTES 10  \
+        CONFIG.SWITCH_PACKET_MODE false  \
+        CONFIG.SWITCH_TDATA_NUM_BYTES 2  \
+        CONFIG.SWITCH_USE_ACLKEN false  \
+        CONFIG.SYNCHRONIZATION_STAGES 2  \
+    ] [get_ips comcellnode_interco]
+
+# Unused properties
+        #CONFIG.C_S00_AXIS_ACLK_RATIO 12 \
+        #CONFIG.C_S00_AXIS_FIFO_DEPTH 32 \
+        #CONFIG.C_S01_AXIS_ACLK_RATIO 12 \
+        #CONFIG.C_S01_AXIS_FIFO_DEPTH 32 \
+        #CONFIG.C_M00_AXIS_FIFO_DEPTH 32 \
+        #CONFIG.C_M00_AXIS_ACLK_RATIO 12 \
+        #CONFIG.C_M00_AXIS_BASETDEST 0x00000000 \
+        #CONFIG.C_M00_AXIS_HIGHTDEST 0x00000000 \
+        #CONFIG.C_SWITCH_TID_WIDTH 1 \
+        #CONFIG.C_SWITCH_TDEST_WIDTH 1 \
+        #CONFIG.SWITCH_TUSER_BITS_PER_BYTE 1 \
+
+set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
+
+# GENERATE AXIS REGISTER SLICE 128 BITS
+set xcipath [create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_reg_128]
+
+set_property -dict [list \
+        CONFIG.HAS_ACLKEN 0 \
+        CONFIG.HAS_TKEEP 0 \
+        CONFIG.HAS_TLAST 0 \
+        CONFIG.HAS_TREADY 1 \
+        CONFIG.HAS_TSTRB 0 \
+        CONFIG.REG_CONFIG 7 \
+        CONFIG.TDATA_NUM_BYTES 16 \
+        CONFIG.TDEST_WIDTH 0 \
+        CONFIG.TID_WIDTH 0 \
+        CONFIG.TUSER_WIDTH 0 \
+    ] [get_ips axis_reg_128]
+
+set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
+
+
+set xcipath [create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name axis_wconv_80_16]
+
+set_property -dict [list \
+    CONFIG.S_TDATA_NUM_BYTES {10} \
+    CONFIG.M_TDATA_NUM_BYTES {2} \
+    CONFIG.HAS_TLAST {1} \
+    CONFIG.TUSER_BITS_PER_BYTE {1}\
+    ] [get_ips axis_wconv_80_16]
+
+set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]