Static numbering offset for the FA sequence.

* Remove pkg_bpmpacket_stream
* now be explicit on fields inside tdata

* Remove check on dummy and reserved field on the frame. Frame is OK
  only of SOP EOP and CRC OK
* When soft reset is set, TVALID stays at zero. Not more packet output
  on AXIS

* Wrong mapping, the _w value was used...

* There were pulses, broken when added a CDC because the pulse was to
  short
* Change of behavior, It is now sticky flags. The register is in the
  inner clock domain, to the CDC handshake is simplier.

* A CDC is now used for PPS input. Fixes double PPS trig and hence rate
  seen as 0
  !! This implies that the PPS signal is at least 2 inner clock cycle
  long

* Break sw  R/RW registers, for OPCUA/ChimeraTK compatibility

* This also reverts commit abcd6a7c.
* Destination logic is on the inner clock domain.
* !! This implies that the PPS signal is at least 2 inner clock cycle
  long.
* update reg doc

* Sometimes 0 were read on the AXI interface. Hopefully this fixes this.

* Break sw  R/RW registers, for OPCUA/ChimeraTK compatibility
* No behavioral change

* Table is now properly aligned
* Remove legacy tready (not used)

* Also change the name of the table.
* DESYRDL right shift the address by 2 before passing it to the memory.
  This is equivalent of having element of 32bits.

* Remove undriven logic in protocol decoder.

* Packet filter is now insed the module
* AXI-MM on its dedicated clock, CDC inside module

* Update doc with recent changes (Clock, filter)
* Module ID is now hardcoded in RDL

Change the project to make it a proper FWK module.

* Or else DESYRDL gives only 9 bits to the decoder, which collides with
the 8 bits address of the table (counted from the 2nd lesser bit)

* Packet filter now uses DESYLIB true dual port RAM.
* Add a packet filter before the module output.
* Add packet filter as external memory in rdl.

* One clock domain for AXI-MM
* One for COM BPM logic
* Xilinx CDC in between (control and status registers).
* Also move component declaration in a package

* Add a README proxy to doc/main.adoc
* Include adoc generated by desyrdl for the register map.
* Frame counters and rates were not linked to the addrmap. Fix that.
* Add description for registers and fields in RDL

* Change the naming in the package and HDL.
* Complete and correct the doc.

* Also remove the ID field

* Use project properties for FPGA part
* Add packet filter to module
* Use packet version

* It does not use it

* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.

* Remove GT interface ready input: useless

* Allow the possibility of counting above 65535