Correction on package usage

hdl/combpm_packet_filter.vhd

@@ -2,7 +2,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-use work.pkg_combpm_stream.all;
+use work.pkg_bpmframe_stream.all;
 
 entity combpm_packet_filter is
     generic(
@@ -134,8 +134,8 @@ architecture rtl of combpm_packet_filter is
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
-    signal in_packet  : t_combpm_axis_packet;
-    signal out_packet : t_combpm_axis_packet;
+    signal in_packet  : t_bpmframe;
+    signal out_packet : t_bpmframe;
 
     signal bram_clk_a : STD_LOGIC;
     signal bram_en_a : STD_LOGIC;
@@ -162,13 +162,13 @@ begin
     p_main: process(axis_clk, axis_rst_n)
     begin
         if axis_rst_n = '0' then
-            in_packet   <= slv2combpmpacket(zero_packet);
-            out_packet  <= slv2combpmpacket(zero_packet);
+            in_packet   <= slv2bpmframe(zero_packet);
+            out_packet  <= slv2bpmframe(zero_packet);
 
         elsif rising_edge(axis_clk) then
             -- Register input packet
             if s_axis_tvalid = '1' then
-                in_packet <= slv2combpmpacket(s_axis_tdata);
+                in_packet <= slv2bpmframe(s_axis_tdata);
             end if;
 
             tvalid_r(tvalid_r'left downto 1) <= tvalid_r(tvalid_r'left-1 downto 0);
@@ -183,7 +183,7 @@ begin
     -- AXIS OUTPUT --
     -----------------
     m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W));
-    m_axis_tdata <= combpmpacket2slv(out_packet);
+    m_axis_tdata <= bpmframe2slv(out_packet);
     m_axis_tlast <= '1';    -- Packet is one tdata only
     m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
 

hdl/combpm_protocol_electron.vhd

@@ -18,7 +18,7 @@ entity combpm_protocol_electron is
 
         -- AXIS interface
         m_axis_m2s         : out t_bpmframe_axis_m2s;
-        m_axis_s2m         : in t_bpmframe_axis_s2m;            -- warning: TREADY is ignored !
+        m_axis_s2m         : in t_bpmframe_axis_s2m;
 
         -- Status and control interface
         soft_reset         : in std_logic;                      -- Reset all counters.
@@ -82,7 +82,7 @@ architecture rtl of combpm_protocol_electron is
     signal rate_valid_r      :  unsigned(31 downto 0);
     signal rate_invalid_r    :  unsigned(31 downto 0);
 
-    signal packet            : t_combpm_axis_packet;
+    signal packet            : t_bpmframe;
     signal m_axi_tvalid      : std_logic;
 
 
@@ -236,7 +236,7 @@ begin
     -- AXIS OUT --
     --------------
     m_axis_m2s.tdest    <= (others => '0');
-    m_axis_m2s.tdata    <= combpmpacket2slv(packet);
+    m_axis_m2s.tdata    <= bpmframe2slv(packet);
     m_axis_m2s.tlast    <= '1'; -- One transfer is One packet.
     m_axis_m2s.tvalid   <= m_axi_tvalid;
 
@@ -244,9 +244,8 @@ begin
     p_axis:process(clk, rst_n)
     begin
         if rst_n = '0' then
-            packet  <= C_PACKET_ZERO;
+            packet  <= C_BPMFRAME_ZERO;
             m_axi_tvalid <= '0';
-            m_axi_tdest  <= (others => '0');
 
         elsif rising_edge(clk) then
 
@@ -258,16 +257,12 @@ begin
                 packet.mc_timestamp <= mc_time;
                 packet.fa_seq       <= packet_timestamp(7 downto 0);
 
-
-                -- AXIS ancillary data
-                m_axi_tdest                 <= packet_bpmid;
-
                 -- AXIS TVALID
                 m_axi_tvalid                <= '1';
             else
 
                 -- Acknowledge transfer
-                if m_axi_tready = '1' then
+                if m_axis_s2m.tready = '1' then
                     m_axi_tvalid            <= '0';
                 end if;
             end if;

hdl/top_combpm_electron.vhd

@@ -13,7 +13,7 @@ library desyrdl;
 use desyrdl.common.all;
 use desyrdl.pkg_combpm.all;
 
-use work.pkg_combpm_stream.all;
+use work.pkg_bpmframe_stream.all;
 use work.pkg_combpm_version.all;
 
 entity top_combpm_electron is
@@ -119,10 +119,10 @@ architecture struct of top_combpm_electron is
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
-    signal sync_resetn   : std_logic;   -- This is async reset with sync deassertion
-    signal sync_reset    : std_logic;   -- This is async reset with sync deassertion
-    signal usrclk        : std_logic;
-    signal rst           : std_logic;
+    signal sync_resetn        : std_logic;   -- This is async reset with sync deassertion
+    signal sync_reset         : std_logic;   -- This is async reset with sync deassertion
+    signal usrclk             : std_logic;
+    signal rst                : std_logic;
 
     signal frame_seq_cnt      : std_logic_vector(15 downto 0);
     signal frame_valid_cnt    : std_logic_vector(31 downto 0);
@@ -141,8 +141,8 @@ architecture struct of top_combpm_electron is
     signal gt_rxbyterealign   : std_logic;
     signal gt_rxcommadet      : std_logic;
 
-    signal addrmap_w    : t_addrmap_combpm_in;
-    signal addrmap_r    : t_addrmap_combpm_out;
+    signal addrmap_w          : t_addrmap_combpm_in;
+    signal addrmap_r          : t_addrmap_combpm_out;
 
 begin
 

tcl/main.tcl

@@ -20,6 +20,7 @@ proc setSources {} {
 
   lappend Vhdl ../hdl/combpm_protocol_electron.vhd
   lappend Vhdl ../hdl/top_combpm_electron.vhd
+  lappend Vhdl ../hdl/pkg_bpmframe_stream.vhd
 
 }