fix: Use a CDC for the PPS

* This also reverts commit abcd6a7c.
* Destination logic is on the inner clock domain.
* !! This implies that the PPS signal is at least 2 inner clock cycle
  long.
* update reg doc

doc/regmap.adoc

@@ -3,34 +3,35 @@
 |===
 |Name | N | bits | type | RW | Description
 
-| ID                                       |    1 |   32 | uint |   RO | +++Module identifier.+++  
-| VERSION                                  |    1 |   32 | uint |   RO | +++Module version.+++  
+| ID                                       |    1 |   32 |     uint | RO | +++Module Identification Number+++ +
+| VERSION                                  |    1 |   32 |     uint | RO | +++Module version.+++ +
 | SFP                                      |    1 |    2 | bitfields |   RO | +++SFP module status+++   +
-- RXLOS [0:0] sw:RO uint : +++RX lost signal+++  +
-- MODABS [1:1] sw:RO uint : +++Module is absent+++   
-| GT                                       |    1 |   11 | bitfields |   RW | +++GT transceivers status and control+++   +
-- POWERGOOD [0:0] sw:RO uint : +++Powergood signal+++  +
-- QPLLLOCK [1:1] sw:RO uint : +++PLL lock signal+++  +
-- RXCLKACTIVE [2:2] sw:RO uint : +++RX clk active signal+++  +
-- RXCDRLOCK [3:3] sw:RO uint : +++RX CDR lock signal+++  +
-- RXRESETDONE [4:4] sw:RO uint : +++RX reset done signal+++  +
-- RXBYTEISALIGNED [5:5] sw:RO uint : +++RX byte is aligned signal+++  +
-- RXBYTEREALIGN [6:6] sw:RO uint : +++RX byte realign signal+++  +
-- RXCOMMADET [7:7] sw:RO uint : +++RX comma detected signal+++  +
-- RXCOMMADETEN [8:8] sw:RW uint : +++RX comma detection enable signal+++  +
-- RXRSTDATAPATH [9:9] sw:RW uint : +++Reset RX datapath+++  +
-- RXRSTPLLDATAPATH [10:10] sw:RW uint : +++Reset RX PLL and datapath+++   
-| PROTOCOL                                 |    1 |    4 | bitfields |   RW | +++BPM protocol status and control+++   +
-- FRAMEERROR [0:0] sw:RO uint : +++Frame error+++  +
-- SEQFRAMECNTERROR [1:1] sw:RO uint : +++Sequence frame count mismatch+++  +
-- SEQFRAMEDISCONT [2:2] sw:RO uint : +++Sequence frame discontinuity+++  +
-- SOFTRESET [3:3] sw:RW uint : +++Soft reset+++   
-| VALIDFRAMECNT                            |    1 |   32 | uint |   RO | +++BPM protocol valid frame counters+++  
-| INVALIDFRAMECNT                          |    1 |   32 | uint |   RO | +++BPM protocol invalid frame counters+++  
-| VALIDFRAMERATE                           |    1 |   32 | uint |   RO | +++BPM protocol valid frame rate+++  
-| INVALIDFRAMERATE                         |    1 |   32 | uint |   RO | +++BPM protocol invalid frame rate+++  
-| FRAMESEQ                                 |    1 |   16 | uint |   RO | +++BPM protocol frame sequence+++  
-| TABLE                                    |  256 |    8 | uint |   RW | +++Packet filter table+++
+    _RXLOS_ [0:0] sw:RO uint : +++RX lost signal+++ +
+    _MODABS_ [1:1] sw:RO uint : +++Module is absent+++ +
+| GT_STATUS                                |    1 |    8 | bitfields | RO | +++GT transceivers status+++ +
+    _POWERGOOD_ [0:0] sw:RO uint : +++Powergood signal+++ +
+    _QPLLLOCK_ [1:1] sw:RO uint : +++PLL lock signal+++ +
+    _RXCLKACTIVE_ [2:2] sw:RO uint : +++RX clk active signal+++ +
+    _RXCDRLOCK_ [3:3] sw:RO uint : +++RX CDR lock signal+++ +
+    _RXRESETDONE_ [4:4] sw:RO uint : +++RX reset done signal+++ +
+    _RXBYTEISALIGNED_ [5:5] sw:RO uint : +++RX byte is aligned signal+++ +
+    _RXBYTEREALIGN_ [6:6] sw:RO uint : +++RX byte realign signal+++ +
+    _RXCOMMADET_ [7:7] sw:RO uint : +++RX comma detected signal+++ +
+| GT_CONTROL                               |    1 |    3 | bitfields | RW | +++GT transceivers control+++ +
+    _RXCOMMADETEN_ [0:0] sw:RW uint : +++RX comma detection enable signal+++ +
+    _RXRSTDATAPATH_ [1:1] sw:RW uint : +++Reset RX datapath+++ +
+    _RXRSTPLLDATAPATH_ [2:2] sw:RW uint : +++Reset RX PLL and datapath+++ +
+| PROTOCOL_ERROR                           |    1 |    3 | bitfields | RO | +++BPM protocol status and control+++ +
+    _FRAMEERROR_ [0:0] sw:RO uint : +++Frame error+++ +
+    _SEQFRAMECNTERROR_ [1:1] sw:RO uint : +++Sequence frame count mismatch+++ +
+    _SEQFRAMEDISCONT_ [2:2] sw:RO uint : +++Sequence frame discontinuity+++ +
+| RESET                                    |    1 |    1 |     uint | RW | +++None+++ +
+| VALIDFRAMECNT                            |    1 |   32 |     uint | RO | +++BPM protocol valid frame counters+++ +
+| INVALIDFRAMECNT                          |    1 |   32 |     uint | RO | +++BPM protocol invalid frame counters+++ +
+| VALIDFRAMERATE                           |    1 |   32 |     uint | RO | +++BPM protocol valid frame rate+++ +
+| INVALIDFRAMERATE                         |    1 |   32 |     uint | RO | +++BPM protocol invalid frame rate+++ +
+| FRAMESEQ                                 |    1 |   16 |     uint | RO | +++BPM protocol frame sequence+++ +
+| FILTERTABLE                              |  256 |   32 | uint | RW | +++BPM filter table+++ +
 |=== 
 
 

hdl/combpm_protocol_electron.vhd

@@ -84,8 +84,6 @@ architecture rtl of combpm_protocol_electron is
     signal packet            : t_bpmpacket;
     signal m_axi_tvalid      : std_logic;
 
-    signal pps_r             : std_logic;
-
 
 begin
 
@@ -289,12 +287,8 @@ begin
             last_cnt_seq_r  <= (others => '0');
             seq_discontinuity <= '0';
             cnt_seq_mismatch    <= '0';
-            pps_r               <= '0';
         elsif rising_edge(clk) then
 
-            -- Register for rising edge filter
-            pps_r       <= pps;
-
             if soft_reset = '1' then
                 cnt_frame_seq_r <= (others => '0');
                 cnt_valid_r     <= (others => '0');
@@ -319,7 +313,7 @@ begin
                 end if;
 
                 -- Rate counter
-                if pps = '1'  and pps_r = '0' then
+                if pps = '1' then
                     frame_valid_rate     <= std_logic_vector(rate_valid_r);
                     frame_invalid_rate   <= std_logic_vector(rate_invalid_r);
                     rate_valid_r    <= (others => '0');

hdl/top_combpm_electron.vhd

@@ -69,6 +69,8 @@ architecture struct of top_combpm_electron is
     signal usrclk             : std_logic;
     signal rst                : std_logic;
 
+    signal pps_resync         : std_logic;
+
     signal frame_seq_cnt      : std_logic_vector(15 downto 0);
     signal frame_valid_cnt    : std_logic_vector(31 downto 0);
     signal frame_invalid_cnt  : std_logic_vector(31 downto 0);
@@ -112,6 +114,21 @@ begin
         src_arst => rst_n
     );
 
+    xpm_cdc_pps_inst: xpm_cdc_pulse
+    generic map (
+        RST_USED => 0,
+        DEST_SYNC_FF => 4,
+        INIT_SYNC_FF => 0
+    )
+    port map (
+        dest_clk    => usrclk,
+        dest_pulse  => pps_resync,
+        src_rst     => '0',
+        dest_rst    => '0',
+        src_clk     => free_100_clk,
+        src_pulse   => pps
+    );
+
 
     -- Reset invert polarity
     rst <= not rst_n;
@@ -232,7 +249,7 @@ begin
     port map(
         rst_n              => sync_resetn,
         clk                => usrclk,
-        pps                => pps,
+        pps                => pps_resync,
         gt_datarx          => gt_datarx,
 
         m_axis_m2s         => m_axis_decoded_m2s,