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Commit b0191881 authored by BRONES Romain's avatar BRONES Romain
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fix Error flags 

* There were pulses, broken when added a CDC because the pulse was to
  short
* Change of behavior, It is now sticky flags. The register is in the
  inner clock domain, to the CDC handshake is simplier.
parent 3b898d76
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hdl/combpm_protocol_electron.vhd
+ 82
− 46
View file @ b0191881
......@@ -20,15 +20,16 @@ entity combpm_protocol_electron is
m_axis_m2s : out t_bpmpacket_axis_m2s;
-- Status and control interface
soft_reset : in std_logic; -- Reset all counters.
frame_seq_cnt : out std_logic_vector(15 downto 0); -- Number of frame in last sequence.
frame_valid_cnt : out std_logic_vector(31 downto 0); -- Count of valid frames.
frame_invalid_cnt : out std_logic_vector(31 downto 0); -- Count of invalid frames.
frame_valid_rate : out std_logic_vector(31 downto 0); -- Valid frame rate.
frame_invalid_rate : out std_logic_vector(31 downto 0); -- Invalid frame rate.
cnt_seq_mismatch : out std_logic; -- Pulse for number of frame in sequence mismatch.
seq_discontinuity : out std_logic; -- Pulse for discontinuity in sequence number.
frame_error : out std_logic -- Pulse for frame error.
soft_reset : in std_logic; -- Reset all counters.
frame_seq_cnt : out std_logic_vector(15 downto 0); -- Number of frame in last sequence.
frame_valid_cnt : out std_logic_vector(31 downto 0); -- Count of valid frames.
frame_invalid_cnt : out std_logic_vector(31 downto 0); -- Count of invalid frames.
frame_valid_rate : out std_logic_vector(31 downto 0); -- Valid frame rate.
frame_invalid_rate : out std_logic_vector(31 downto 0); -- Invalid frame rate.
flag_cnt_seq_mismatch : out std_logic; -- Number of frame in sequence mismatch.
flag_seq_discontinuity : out std_logic; -- Discontinuity in sequence number.
flag_frame_error : out std_logic; -- Frame error.
flag_reset : in std_logic -- Reset all flags.
);
end entity combpm_protocol_electron;
......@@ -46,47 +47,82 @@ architecture rtl of combpm_protocol_electron is
------------------------
-- SIGNAL DECLARATION --
------------------------
signal packet_reg : std_logic_vector(14*16-1 downto 0); -- Register to hold one packet
signal flag_sop_inc : std_logic;
signal flag_sop : std_logic;
signal flag_eop : std_logic;
signal flag_dummy : std_logic;
signal flag_rsvd : std_logic;
signal flag_crc : std_logic;
signal flag_all : std_logic;
signal flag_frame : std_logic;
signal packet_bpmid : std_logic_vector(9 downto 0);
signal packet_startframe : std_logic;
signal packet_timestamp : std_logic_vector(15 downto 0);
signal packet_xpos : std_logic_vector(31 downto 0);
signal packet_ypos : std_logic_vector(31 downto 0);
signal packet_crc : std_logic_vector(31 downto 0);
signal crc_result : std_logic_vector(31 downto 0);
signal xorinv_crc_reg : std_logic_vector(31 downto 0);
signal inv_crc_reg : std_logic_vector(31 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal lfsr_c : std_logic_vector(31 downto 0);
signal crc_cnt : unsigned(3 downto 0);
signal d : std_logic_vector(15 downto 0);
signal last_seq : std_logic_vector(15 downto 0);
signal last_cnt_seq_r : unsigned(15 downto 0);
signal cnt_frame_seq_r : unsigned(15 downto 0);
signal cnt_valid_r : unsigned(31 downto 0);
signal cnt_invalid_r : unsigned(31 downto 0);
signal rate_valid_r : unsigned(31 downto 0);
signal rate_invalid_r : unsigned(31 downto 0);
signal packet : t_bpmpacket;
signal m_axi_tvalid : std_logic;
signal packet_reg : std_logic_vector(14*16-1 downto 0); -- Register to hold one packet
signal flag_sop_inc : std_logic;
signal flag_sop : std_logic;
signal flag_eop : std_logic;
signal flag_dummy : std_logic;
signal flag_rsvd : std_logic;
signal flag_crc : std_logic;
signal flag_all : std_logic;
signal flag_frame : std_logic;
signal packet_bpmid : std_logic_vector(9 downto 0);
signal packet_startframe : std_logic;
signal packet_timestamp : std_logic_vector(15 downto 0);
signal packet_xpos : std_logic_vector(31 downto 0);
signal packet_ypos : std_logic_vector(31 downto 0);
signal packet_crc : std_logic_vector(31 downto 0);
signal crc_result : std_logic_vector(31 downto 0);
signal xorinv_crc_reg : std_logic_vector(31 downto 0);
signal inv_crc_reg : std_logic_vector(31 downto 0);
signal crc_reg : std_logic_vector(31 downto 0);
signal lfsr_c : std_logic_vector(31 downto 0);
signal crc_cnt : unsigned(3 downto 0);
signal d : std_logic_vector(15 downto 0);
signal last_seq : std_logic_vector(15 downto 0);
signal last_cnt_seq_r : unsigned(15 downto 0);
signal cnt_frame_seq_r : unsigned(15 downto 0);
signal cnt_valid_r : unsigned(31 downto 0);
signal cnt_invalid_r : unsigned(31 downto 0);
signal rate_valid_r : unsigned(31 downto 0);
signal rate_invalid_r : unsigned(31 downto 0);
signal packet : t_bpmpacket;
signal m_axi_tvalid : std_logic;
signal cnt_seq_mismatch : std_logic;
signal seq_discontinuity : std_logic;
signal frame_error : std_logic;
begin
------------------------
-- STICKY ERROR FLAGS --
------------------------
p_stickerr:process(clk, rst_n)
begin
if rst_n = '0' then
flag_cnt_seq_mismatch <= '0';
flag_seq_discontinuity <= '0';
flag_frame_error <= '0';
elsif rising_edge(clk) then
if flag_reset = '1' then
flag_cnt_seq_mismatch <= '0';
flag_seq_discontinuity <= '0';
flag_frame_error <= '0';
else
if cnt_seq_mismatch = '1' then
flag_cnt_seq_mismatch <= '1';
end if;
if seq_discontinuity = '1' then
flag_seq_discontinuity <= '1';
end if;
if frame_error = '1' then
flag_frame_error <= '1';
end if;
end if;
end if;
end process;
---------------------
-- PACKET REGISTER --
---------------------
......
hdl/top_combpm_electron.vhd
+ 19
− 17
View file @ b0191881
......@@ -79,6 +79,7 @@ architecture struct of top_combpm_electron is
signal cnt_seq_mismatch : std_logic;
signal seq_discontinuity : std_logic;
signal frame_error : std_logic;
signal flag_reset : std_logic;
signal gt_datarx : std_logic_vector(15 downto 0);
signal gt_powergood : std_logic;
......@@ -247,23 +248,24 @@ begin
--------------------------------------
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => sync_resetn,
clk => usrclk,
pps => pps_resync,
gt_datarx => gt_datarx,
m_axis_m2s => m_axis_decoded_m2s,
mc_time => mc_time,
soft_reset => addrmap_w.RESET.SOFTRESET.data(0),
frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt,
frame_invalid_cnt => frame_invalid_cnt,
frame_valid_rate => frame_valid_rate,
frame_invalid_rate => frame_invalid_rate,
cnt_seq_mismatch => cnt_seq_mismatch,
seq_discontinuity => seq_discontinuity,
frame_error => frame_error
rst_n => sync_resetn,
clk => usrclk,
pps => pps_resync,
gt_datarx => gt_datarx,
m_axis_m2s => m_axis_decoded_m2s,
mc_time => mc_time,
soft_reset => addrmap_w.RESET.SOFTRESET.data(0),
frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt,
frame_invalid_cnt => frame_invalid_cnt,
frame_valid_rate => frame_valid_rate,
frame_invalid_rate => frame_invalid_rate,
flag_cnt_seq_mismatch => cnt_seq_mismatch,
flag_seq_discontinuity => seq_discontinuity,
flag_frame_error => frame_error,
flag_reset => addrmap_w.RESET_ERROR.SOFTRESET.data(0)
);
---------------
......
rdl/combpm.rdl
+ 5
− 0
View file @ b0191881
......@@ -63,6 +63,11 @@ addrmap combpm {
field {desc="Sequence frame discontinuity";} SEQFRAMEDISCONT;
} PROTOCOL_ERROR;
reg {
default sw = rw; default hw = r;
field {desc="Reset error flags";} SOFTRESET;
} RESET_ERROR;
reg {
default sw = rw; default hw = r;
field {desc="Soft reset";} SOFTRESET;
......
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