fix Error flags

* There were pulses, broken when added a CDC because the pulse was to
  short
* Change of behavior, It is now sticky flags. The register is in the
  inner clock domain, to the CDC handshake is simplier.

hdl/combpm_protocol_electron.vhd

@@ -26,9 +26,10 @@ entity combpm_protocol_electron is
         frame_invalid_cnt       : out std_logic_vector(31 downto 0); -- Count of invalid frames.
         frame_valid_rate        : out std_logic_vector(31 downto 0); -- Valid frame rate.
         frame_invalid_rate      : out std_logic_vector(31 downto 0); -- Invalid frame rate.
-        cnt_seq_mismatch   : out std_logic;                     -- Pulse for number of frame in sequence mismatch.
-        seq_discontinuity  : out std_logic;                     -- Pulse for discontinuity in sequence number.
-        frame_error        : out std_logic                      -- Pulse for frame error.
+        flag_cnt_seq_mismatch   : out std_logic;                     -- Number of frame in sequence mismatch.
+        flag_seq_discontinuity  : out std_logic;                     -- Discontinuity in sequence number.
+        flag_frame_error        : out std_logic;                     -- Frame error.
+        flag_reset              : in std_logic                       -- Reset all flags.
     );
 end entity combpm_protocol_electron;
 
@@ -84,9 +85,44 @@ architecture rtl of combpm_protocol_electron is
     signal packet                   : t_bpmpacket;
     signal m_axi_tvalid             : std_logic;
 
+    signal cnt_seq_mismatch         : std_logic;
+    signal seq_discontinuity        : std_logic;
+    signal frame_error              : std_logic;
+
 
 begin
 
+
+    ------------------------
+    -- STICKY ERROR FLAGS --
+    ------------------------
+    p_stickerr:process(clk, rst_n)
+    begin
+        if rst_n = '0' then
+            flag_cnt_seq_mismatch           <= '0';
+            flag_seq_discontinuity          <= '0';
+            flag_frame_error                <= '0';
+        elsif rising_edge(clk) then
+
+            if flag_reset = '1' then
+                flag_cnt_seq_mismatch       <= '0';
+                flag_seq_discontinuity      <= '0';
+                flag_frame_error            <= '0';
+            else
+                if cnt_seq_mismatch = '1' then
+                    flag_cnt_seq_mismatch   <= '1';
+                end if;
+                if seq_discontinuity = '1' then
+                    flag_seq_discontinuity  <= '1';
+                end if;
+                if frame_error = '1' then
+                    flag_frame_error        <= '1';
+                end if;
+            end if;
+        end if;
+    end process;
+
+
     ---------------------
     -- PACKET REGISTER --
     ---------------------

hdl/top_combpm_electron.vhd

@@ -79,6 +79,7 @@ architecture struct of top_combpm_electron is
     signal cnt_seq_mismatch   : std_logic;
     signal seq_discontinuity  : std_logic;
     signal frame_error        : std_logic;
+    signal flag_reset         : std_logic;
 
     signal gt_datarx          : std_logic_vector(15 downto 0);
     signal gt_powergood       : std_logic;
@@ -261,9 +262,10 @@ begin
         frame_invalid_cnt       => frame_invalid_cnt,
         frame_valid_rate        => frame_valid_rate,
         frame_invalid_rate      => frame_invalid_rate,
-        cnt_seq_mismatch   => cnt_seq_mismatch,
-        seq_discontinuity  => seq_discontinuity,
-        frame_error        => frame_error
+        flag_cnt_seq_mismatch   => cnt_seq_mismatch,
+        flag_seq_discontinuity  => seq_discontinuity,
+        flag_frame_error        => frame_error,
+        flag_reset              => addrmap_w.RESET_ERROR.SOFTRESET.data(0)
     );
 
     ---------------

rdl/combpm.rdl

@@ -63,6 +63,11 @@ addrmap combpm {
         field {desc="Sequence frame discontinuity";} SEQFRAMEDISCONT;
     } PROTOCOL_ERROR;
 
+    reg  {
+        default sw = rw; default hw = r;
+        field {desc="Reset error flags";} SOFTRESET;
+    } RESET_ERROR;
+
     reg  {
         default sw = rw; default hw = r;
         field {desc="Soft reset";} SOFTRESET;