COMBPM module documentation
MODULE ID |
0x507E1710 |
(1350440720) |
Description
This module provides several logic blocks to allow communication with BPM (Beam Position Monitor) electronics. This has been built for a very precise situation (libera electron, damc-fmc2zup), but the architecture should allow modification and portability.
For now, it only provides RX communication from the DLS CC protocol (ITech libera electron). The module has been designed for DAMC-FMC2ZUP targets, populated with a 4SFP+ FMC board (CAENels).
Requires DESY VHDL LIB (dual port ram)
Overview
Main operation: Top level
The basics of this module is in four blocs that are essentials for the application.
-
Transceiver bloc. Used to deserialize the communication stream from the BPM.
For now it is a Xilinx GTWizard, configured for the Libera Electron DLS CC protocol specs (2Gbps, 16b words…). This is tied to a specific transceiver input (X0Y4) of the FPGA. -
Protocol decoder bloc. From the deserialized words, it decode the stream and get the essential data (BPM number, position, timestamp…). It outputs it on a AXI-Stream interface.
For now, it parses Libera Electron DLS CC. -
Packet filter. Filter packets based on the BPMID and can translate a value to the TDEST field of the AXIS output.
-
AXI-MM register interface. Used to configure and monitor everything from an AXI-MM interface (CPU).
These three blocs are depicted in the image below.
It is to note that the clock domain used is the data clock, even for the register interface.
This clock is provided and can be used to clock the rest of the application and/or clock CDC on the AXI-MM and AXIS interface.
The actual top_combpm_electron.vhd file provides these three blocs configured and connected for the Libera Electron and damc-fmc2zup application.
Details
Protocol decoder (electron)
-
CRC check. If fails: drop the frame, pulse frame_error output and increase the error counter.
-
Counts and gives the number of frame in the last DLS CC sequence receive.
-
DLS CC Sequence number check. If discontinuous: pulse seq_discontinuity output and increase
BPM packet AXIS stream
-
Packets are not cut into packets (TLAST always '1').
-
No FIFO on output (TREADY is not used). The application needs to either implement FIFO or accepts every packet (AXIS packet). The packet rate depends on the signal input.
Transceivers
The TCL script combpm_gtwizard.tcl is used to create the GTWizard IP, wich is instanciated in the top level.
Packet filter
This block can drop BPM packets from the AXIS by looking up their BPM_ID field. A simple memory block is used and programmed via the AXI-MM interface. The block is addressed by the BPM ID (0 to 255).
The msb (bit 7) gives the forward signal. If '1' then the packet is transfered, else it is blocked.
The 6 lsb (bit 6-0) is filled into the TDEST field of the AXIS stream. This can be used to further routing.
Registers map
| Name | N | bits | type | RW | Description |
|---|---|---|---|---|---|
ID |
1 |
32 |
uint |
RO |
Module Identification Number |
VERSION |
1 |
32 |
uint |
RO |
Module version. |
SFP |
1 |
2 |
bitfields |
RO |
SFP module status |
GT_STATUS |
1 |
8 |
bitfields |
RO |
GT transceivers status |
GT_CONTROL |
1 |
3 |
bitfields |
RW |
GT transceivers control |
PROTOCOL_ERROR |
1 |
3 |
bitfields |
RO |
BPM protocol status and control |
RESET_ERROR |
1 |
1 |
uint |
RW |
None |
RESET |
1 |
1 |
uint |
RW |
None |
VALIDFRAMECNT |
1 |
32 |
uint |
RO |
BPM protocol valid frame counters |
INVALIDFRAMECNT |
1 |
32 |
uint |
RO |
BPM protocol invalid frame counters |
VALIDFRAMERATE |
1 |
32 |
uint |
RO |
BPM protocol valid frame rate |
INVALIDFRAMERATE |
1 |
32 |
uint |
RO |
BPM protocol invalid frame rate |
FRAMESEQ |
1 |
16 |
uint |
RO |
BPM protocol frame sequence |
SEQ_OFFSET |
1 |
16 |
int16 |
RW |
Sequence numbering offset |
FILTERTABLE |
256 |
32 |
uint |
RW |
BPM filter table |