* Sometimes 0 were read on the AXI interface. Hopefully this fixes this.

* Break sw  R/RW registers, for OPCUA/ChimeraTK compatibility
* No behavioral change

* Also change the name of the table.
* DESYRDL right shift the address by 2 before passing it to the memory.
  This is equivalent of having element of 32bits.

* Remove undriven logic in protocol decoder.

* Update doc with recent changes (Clock, filter)
* Module ID is now hardcoded in RDL

* Packet filter now uses DESYLIB true dual port RAM.
* Add a packet filter before the module output.
* Add packet filter as external memory in rdl.

* One clock domain for AXI-MM
* One for COM BPM logic
* Xilinx CDC in between (control and status registers).
* Also move component declaration in a package

* Add a README proxy to doc/main.adoc
* Include adoc generated by desyrdl for the register map.
* Frame counters and rates were not linked to the addrmap. Fix that.
* Add description for registers and fields in RDL

* Change the naming in the package and HDL.
* Complete and correct the doc.

* Also remove the ID field

* It does not use it

* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.

* Remove GT interface ready input: useless

* Allow the possibility of counting above 65535

* the y position received the x data :(

Packet Filter
* Address width for memory is now a generic
* This width is a parameter for generation of xilinx ips
* fix for synthesis

COMBPM
* use package for COMBPM packet

package COMBPM
* new constant for zero packet

* Do not allow to start CRC computation right after a result
* CRC word counter up to 12 then roll over to 0

* Need at least SOP and EOP.
* If any other flag is missing, raise error

* Error detect can trigger an interrupt, a capture...
* More debug to understand situations

* Reset the register properly
* Add register in memory map bank

Top level:
* Add MC time and PPS port
* GT Interface ready combinatorial inside top level

Protocol decoder
* New GT Interface ready input port
* New MC time and PPS input ports
* New output ports for new features
* Frame counters, frame rates
* Sequence checkers
* Change output AXIS packet : MC time, packet_time LSB only

AXI interface:
* Add registers for new features
* Fix Makefile rule for RDL->VHD

* Add debug ports of transceiver data and status before the protocole
  decoder.
* Add a reset bit for PLL and datapath in AXI-MM interface.

* Connect true QPLL lock bit
* Attribute on QPLL_reset is now active high

* Remove unused signals

Also add Makefile rule to perform synthesis of IP bloc

* GTHE COMMON must be outside IP (QPLL needed for other interfaces)
* GTWizard created with TCL
* GTWizard instantiated directly in top level

VHDL
* Add attributes on interface ports.
* Bring back QPLL andCDR lock signals on the GT wrapper

TCL
* Add simple address map

* Use a makefile to build the packaged IP

* Corrections for synthesis
* QPLL lock output signal TEMPORARY set to one   !!

* Use a package