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Commit 5e9a037b authored by BRONES Romain's avatar BRONES Romain
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VHDL fixes 

Packet Filter
* Address width for memory is now a generic
* This width is a parameter for generation of xilinx ips
* fix for synthesis

COMBPM
* use package for COMBPM packet

package COMBPM
* new constant for zero packet
parent 4947e567
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hdl/combpm_packet_filter.vhd
+ 16
− 12
View file @ 5e9a037b
......@@ -5,6 +5,9 @@ use ieee.numeric_std.all;
use work.pkg_combpm_stream.all;
entity combpm_packet_filter is
generic(
G_B_ADDR_W : natural := 14
);
port(
axis_clk : in std_logic;
axi_clk : in std_logic;
......@@ -26,7 +29,7 @@ entity combpm_packet_filter is
m_axis_tready : in std_logic;
-- AXI bus interface
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
......@@ -43,7 +46,7 @@ entity combpm_packet_filter is
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
......@@ -70,7 +73,7 @@ architecture rtl of combpm_packet_filter is
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
......@@ -87,7 +90,7 @@ architecture rtl of combpm_packet_filter is
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
......@@ -105,7 +108,7 @@ architecture rtl of combpm_packet_filter is
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
......@@ -116,13 +119,13 @@ architecture rtl of combpm_packet_filter is
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
......@@ -137,7 +140,7 @@ architecture rtl of combpm_packet_filter is
signal bram_clk_a : STD_LOGIC;
signal bram_en_a : STD_LOGIC;
signal bram_we_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal bram_addr_a : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal bram_addr_a : STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
signal bram_wrdata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal bram_rddata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
......@@ -179,7 +182,7 @@ begin
-----------------
-- AXIS OUTPUT --
-----------------
m_axis_tdest <= std_logic_vector(risize(unsigned(table_data(6 downto 0)), C_TDEST_W));
m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W));
m_axis_tdata <= combpmpacket2slv(out_packet);
m_axis_tlast <= '1'; -- Packet is one tdata only
m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
......@@ -228,7 +231,8 @@ begin
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_addr_a(1 downto 0) => open,
bram_addr_a(G_B_ADDR_W-1 downto 2) => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a
);
......@@ -246,8 +250,8 @@ begin
douta => bram_rddata_a,
clkb => axis_clk,
enb => '1',
web => '0',
addrb => in_packet.bpm_id(9 downto 0),
web => "0",
addrb => in_packet.bpm_id(G_B_ADDR_W-1 downto 0),
dinb => (others => '0'),
doutb => table_data
);
......
hdl/combpm_protocol_electron.vhd
+ 12
− 6
View file @ 5e9a037b
......@@ -3,6 +3,8 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_combpm_stream.all;
entity combpm_protocol_electron is
port(
rst_n : in std_logic;
......@@ -88,6 +90,8 @@ architecture rtl of combpm_protocol_electron is
signal rate_valid_r : unsigned(15 downto 0);
signal rate_invalid_r : unsigned(15 downto 0);
signal packet : t_combpm_axis_packet;
begin
......@@ -244,11 +248,12 @@ begin
m_axi_tid <= "0";
m_axi_tuser <= "0";
m_axi_tlast <= '1'; -- One transfer is One packet.
m_axi_tdata <= combpmpacket2slv(packet);
p_axis:process(clk, rst_n)
begin
if rst_n = '0' then
m_axi_tdata <= (others => '0');
packet <= C_PACKET_ZERO;
m_axi_tvalid <= '0';
m_axi_tdest <= (others => '0');
......@@ -256,11 +261,12 @@ begin
if flag_all = '1' then
-- Make AXIS packet
m_axi_tdata(31 downto 0) <= packet_ypos;
m_axi_tdata(63 downto 32) <= packet_xpos;
m_axi_tdata(103 downto 64) <= mc_time;
m_axi_tdata(111 downto 104) <= packet_timestamp(7 downto 0);
m_axi_tdata(127 downto 112) <= "000000" & packet_bpmid;
packet.pos_x <= packet_xpos;
packet.pos_y <= packet_xpos;
packet.bpm_id <= "000000" & packet_bpmid;
packet.mc_timestamp <= mc_time;
packet.fa_seq <= packet_timestamp(7 downto 0);
-- AXIS ancillary data
m_axi_tdest <= packet_bpmid;
......
hdl/pkg_combpm_stream.vhd
+ 11
− 1
View file @ 5e9a037b
......@@ -3,7 +3,9 @@ use ieee.std_logic_1164.all;
package pkg_combpm_stream is
-- CONSTANT
----------------------
-- MACRO PARAMETERS --
----------------------
constant C_TDEST_W : natural := 7;
constant C_TDATA_W : natural := 128;
......@@ -41,6 +43,14 @@ package pkg_combpm_stream is
fa_seq : std_logic_vector(7 downto 0);
end record t_combpm_axis_packet;
constant C_PACKET_ZERO : t_combpm_axis_packet := (
pos_x => (others => '0'),
pos_y => (others => '0'),
bpm_id => (others => '0'),
mc_timestamp => (others => '0'),
fa_seq => (others => '0')
);
function slv2combpmpacket(
signal tdata : std_logic_vector(C_TDATA_W-1 downto 0)
)
......
tcl/generate_combpm_packet_filter_ip.tcl
+ 16
− 3
View file @ 5e9a037b
# Address width, on logic side (8 bits data access)
set b_addr_w 14
# Address width on AXI MM side (32 bits access)
set a_addr_w [expr $b_addr_w-2]
set a_depth [expr 1<<$a_addr_w]
set b_depth [expr 1<<$b_addr_w]
set xcipath [create_ip -name axi_bram_ctrl -vendor xilinx.com -library ip -version 4.1 -module_name combpm_packet_filter_axi_bram_ctrl]
set_property -dict [list \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.SINGLE_PORT_BRAM {1} \
CONFIG.ECC_TYPE {0} \
CONFIG.USE_ECC {0} \
CONFIG.BMG_INSTANCE {EXTERNAL} \
CONFIG.MEM_DEPTH {16384} \
CONFIG.MEM_DEPTH $a_depth \
CONFIG.CLKIF.FREQ_HZ 250000000 \
CONFIG.DATA_WIDTH 32 \
] [get_ips combpm_packet_filter_axi_bram_ctrl]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
......@@ -18,7 +31,7 @@ set_property -dict [list \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Byte_Size {8} \
CONFIG.Write_Width_A {32} \
CONFIG.Write_Depth_A {16384} \
CONFIG.Write_Depth_A $a_depth \
CONFIG.Read_Width_A {32} \
CONFIG.Operating_Mode_A {WRITE_FIRST} \
CONFIG.Write_Width_B {8} \
......
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