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Commit a63e2aab authored by BRONES Romain's avatar BRONES Romain
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Modification and correction for integration 

VHDL
* Add attributes on interface ports.
* Bring back QPLL andCDR lock signals on the GT wrapper

TCL
* Add simple address map
parent 5084a443
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hdl/combpm_gtwrapper.vhd
+ 1
− 0
View file @ a63e2aab
......@@ -45,6 +45,7 @@ entity combpm_gtwrapper is
gt_rxbyteisaligned : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxbyterealign : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcommadet : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcdrlock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txfault : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxlos : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_modabs : out std_logic_vector(C_NUM_CHAN-1 downto 0);
......
hdl/top_combpm_electron.vhd
+ 27
− 13
View file @ a63e2aab
......@@ -13,9 +13,9 @@ entity top_combpm_electron is
free_100_clk : in std_logic; -- Freerunning clock for GT
-- Differential reference clock inputs and buffered output
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
mgtrefclk : out std_logic;
mgtref_clk_p : in std_logic;
mgtref_clk_n : in std_logic;
mgtref_buf_clk : out std_logic;
-- SFP interfaces
sfp_txp : out std_logic;
......@@ -73,10 +73,22 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
ATTRIBUTE X_INTERFACE_PARAMETER of gt_clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi, ASSOCIATED_RESET rst_n";
ATTRIBUTE X_INTERFACE_PARAMETER of mgtref_buf_clk: SIGNAL is "FREQ_HZ 156250000";
ATTRIBUTE X_INTERFACE_PARAMETER of gt_clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
ATTRIBUTE X_INTERFACE_INFO of sfp_txn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_txp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rx_los: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp_mod_abs: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of mgtref_clk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 mgtrefclk CLK_P";
ATTRIBUTE X_INTERFACE_INFO of mgtref_clk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 mgtrefclk CLK_N";
ATTRIBUTE X_INTERFACE_PARAMETER of mgtref_clk_p: SIGNAL is "FREQ_HZ 156250000";
--ATTRIBUTE X_INTERFACE_INFO of free_100_clk : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
------------------------
-- SIGNAL DECLARATION --
......@@ -89,7 +101,7 @@ architecture struct of top_combpm_electron is
signal frame_counter : std_logic_vector(15 downto 0);
signal frame_error : std_logic;
signal gt_userclk : std_logic;
signal gt_usrclk : std_logic;
signal gt_datarx : std_logic_vector(15 downto 0);
signal gt_datatx : std_logic_vector(15 downto 0);
signal gt_powergood : std_logic;
......@@ -107,6 +119,7 @@ architecture struct of top_combpm_electron is
signal gt_rstall : std_logic;
signal gt_rxcommadeten : std_logic;
signal gt_txdisable : std_logic;
signal gt_rxcdrlock : std_logic;
begin
......@@ -179,7 +192,7 @@ begin
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => rst_n,
clk => gt_userclk,
clk => gt_usrclk,
gt_datarx => gt_datarx,
gt_datatx => gt_datatx,
gt_powergood => gt_powergood,
......@@ -220,22 +233,22 @@ begin
----------------
-- GT WRAPPER --
----------------
gt_clk <= gt_userclk;
gt_clk <= gt_usrclk;
inst_gtwrapper: entity work.combpm_gtwrapper
port map(
-- 100MHz clock, main ref clock
clk_100 => clk_100,
clk_100 => free_100_clk,
-- Usrclock for data transfer
usrclk => gt_userclk,
usrclk => gt_usrclk,
-- Async reset active low
rst_n => rst_n,
-- Differential reference clock inputs and buffered output
mgtrefclk_p => mgtrefclk_p,
mgtrefclk_n => mgtrefclk_n,
mgtrefclk => open,
mgtrefclk_p => mgtref_clk_p,
mgtrefclk_n => mgtref_clk_n,
mgtrefclk => mgtref_buf_clk,
-- SFP interfaces
sfp_txp(0) => sfp_txp,
......@@ -261,6 +274,7 @@ begin
gt_rxcommadet(0) => gt_rxcommadet,
gt_txfault(0) => gt_txfault,
gt_rxlos(0) => gt_rxlos,
gt_rxcdrlock(0) => gt_rxcdrlock,
gt_modabs(0) => gt_modabs,
gt_rstall(0) => gt_rstall,
gt_rxcommadeten(0) => gt_rxcommadeten,
......
tcl/combpm.tcl
+ 18
− 1
View file @ a63e2aab
......@@ -19,9 +19,26 @@ set_property -dict ${ip_properties} ${ip_core}
set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
# Associate AX/AXIS interfaces and reset with clock
# Later... or in HDL
# Done in VHDL file
# Create Address map
set s_axi_mm [ipx::add_memory_map s_axi_ctrl [ipx::current_core]]
set_property slave_memory_map_ref s_axi_ctrl [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
set_property ENABLEMENT_PRESENCE required ${s_axi_mm}
set s_axi_blk [ipx::add_address_block registers ${s_axi_mm}]
set_property -dict { \
ACCESS "read-write" \
DESCRIPTION "Control and status registers" \
ENABLEMENT_PRESENCE required \
NAME "registers" \
RANGE 256 \
USAGE "register" \
WIDTH 8 \
} ${s_axi_blk}
# Save IP and close project
ipx::check_integrity ${ip_core}
ipx::save_core ${ip_core}
close_project
file delete -force ${proj_dir}
xci/CAENELS4SFP_1L.xci
+ 8
− 7
View file @ a63e2aab
......@@ -6,7 +6,7 @@
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>CAENELSSFP_1L</spirit:instanceName>
<spirit:instanceName>combpm_gtwrapper</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard_ultrascale" spirit:version="1.7"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CHANNEL_ENABLE">&quot;000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000&quot;</spirit:configurableElementValue>
......@@ -44,7 +44,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_K">&quot;00000011&quot;</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_LEN_SEQ">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_NUM_SEQ">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_PERIODICITY">5000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_PERIODICITY">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_CC_VAL">&quot;00000000000000000000000000000000000000000000000000000000000000100101010010111100&quot;</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_COMMA_M_ENABLE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RX_COMMA_M_VAL">&quot;1010000011&quot;</spirit:configurableElementValue>
......@@ -102,10 +102,10 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TX_USRCLK_FREQUENCY">106.0000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_GTPOWERGOOD_DELAY_EN">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE">X0Y4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">CAENELSSFP_1L</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">combpm_gtwrapper</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_LOC_XDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_COMMON_USRCLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS"/>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS">qpll1lock_out rxcdrlock_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FREERUN_FREQUENCY">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_DIRECTION">BOTH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GT_REV">0</spirit:configurableElementValue>
......@@ -651,7 +651,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBMDMTDO_OUT">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBRSVDOUT_OUT">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLED_UBTXUART_OUT">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">20</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_ENABLEMENT_UPDATED">21</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PORT_USAGE_UPDATED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_PRESET">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERNAL_RX_COMMA_PRESET_UPDATE">7</spirit:configurableElementValue>
......@@ -1041,7 +1041,7 @@
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxbyterealign_out">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrfreqreset_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrhold_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrlock_out">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrlock_out">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrovrden_in">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrphdone_out">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PORT_ENABLEMENT.rxcdrreset_in">false</spirit:configurableElementValue>
......@@ -1369,7 +1369,7 @@
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../damc_fmc2zup_project.gen/sources_1/ip/CAENELSSFP_1L</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../../../../project/damc_fmc2zup_project.tmp/combpm_v1_0_project/combpm_v1_0_project.gen/sources_1/ip/combpm_gtwrapper</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2020.2</spirit:configurableElementValue>
......@@ -1379,6 +1379,7 @@
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CHANNEL_ENABLE" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_OPTIONAL_PORTS" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FREERUN_FREQUENCY" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_RX_USER_CLOCKING" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.LOCATE_TX_USER_CLOCKING" xilinx:valueSource="user"/>
......
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