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Commit 5084a443 authored by BRONES Romain's avatar BRONES Romain
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Add script to package the IP 

* Use a makefile to build the packaged IP
parent 77c9f750
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Makefile 0 → 100644
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###############################################################################
# Global receipes
none:
$(info You should specify what to make: ip, sim, clean, clean-all)
ip:component.xml
sim:
###############################################################################
# Configuration
# TODO: better way to configure ?
hdlpkgsrc := hdl_pkg/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd
xcisrc := xci/CAENELS4SFP_1L.xci
###############################################################################
# Generate a source list, depending on the config
rdlsrc := $(shell ls rdl/*.rdl)
rdltarget := $(rdlsrc:rdl/%.rdl=hdl/%.vhd)
hdlsrc := $(shell ls hdl/*.vhd) $(rdltarget) $(hdlpkgsrc)
# TODO: depends on the configuration
tcl/sources.tcl:
echo read_vhdl {$(hdlsrc)} > $@
echo import_ip -name combpm_gtwrapper $(xcisrc) >> $@
###############################################################################
# Compute interface from rdl files
# TODO: generic rule from variables
hdl/combpm_protocol_electron_ctrl.vhd: rdl/combpm_protocol_electron_ctrl.rdl
hectare --axi-vhdl $@ $<
###############################################################################
# Package IP
component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc) $(xcisrc)
vivado -mode batch -source tcl/combpm.tcl
###############################################################################
# Cleaner Rules
clean:
rm -f vivado*.log vivado*.jou
clean-ip:
rm -rf ip_proj ip_user_files xgui
rm -f component.xml
clean-sim:
rm -f *.wdb
clean-all:clean-ip clean
rm -f tcl/sources.tcl
hdl/combpm_protocol_electron_ctrl.vhd deleted 100644 → 0
+ 0
− 346
View file @ 77c9f750
-- This file was automatically generated with HECTARE
--
-- DO NOT EDIT
--
-- input_filename = combpm_protocol_electron_ctrl.rdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity combpm_protocol_electron_ctrl_axi is
generic(
G_ADDR_W: integer := 8
);
port (
sfp_txfault_i : in std_logic;
sfp_rxlos_i : in std_logic;
sfp_modabs_i : in std_logic;
sfp_txdisable_o : out std_logic;
gt_powergood_i : in std_logic;
gt_qplllock_i : in std_logic;
gt_txclkactive_i : in std_logic;
gt_rxclkactive_i : in std_logic;
gt_rxcdrlock_i : in std_logic;
gt_txresetdone_i : in std_logic;
gt_rxresetdone_i : in std_logic;
gt_rxbyteisaligned_i : in std_logic;
gt_rxbyterealign_i : in std_logic;
gt_rxcommadet_i : in std_logic;
gt_rxcommadeten_o : out std_logic;
gt_rstall_o : out std_logic;
protocol_framecnt_i : in std_logic_vector(15 downto 0);
protocol_frameerror_i : in std_logic;
clk : in std_logic;
reset : in std_logic;
S_AXI_AWADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end entity;
architecture arch of combpm_protocol_electron_ctrl_axi is
-- address constants
constant C_ADDR_SFP : integer := 0;
constant C_ADDR_GT : integer := 1;
constant C_ADDR_PROTOCOL : integer := 2;
-- field ranges constants
constant C_FIELD_SFP_TXFAULT_MSB : integer := 0;
constant C_FIELD_SFP_TXFAULT_LSB : integer := 0;
constant C_FIELD_SFP_RXLOS_MSB : integer := 1;
constant C_FIELD_SFP_RXLOS_LSB : integer := 1;
constant C_FIELD_SFP_MODABS_MSB : integer := 2;
constant C_FIELD_SFP_MODABS_LSB : integer := 2;
constant C_FIELD_SFP_TXDISABLE_MSB : integer := 3;
constant C_FIELD_SFP_TXDISABLE_LSB : integer := 3;
constant C_FIELD_GT_POWERGOOD_MSB : integer := 0;
constant C_FIELD_GT_POWERGOOD_LSB : integer := 0;
constant C_FIELD_GT_QPLLLOCK_MSB : integer := 1;
constant C_FIELD_GT_QPLLLOCK_LSB : integer := 1;
constant C_FIELD_GT_TXCLKACTIVE_MSB : integer := 2;
constant C_FIELD_GT_TXCLKACTIVE_LSB : integer := 2;
constant C_FIELD_GT_RXCLKACTIVE_MSB : integer := 3;
constant C_FIELD_GT_RXCLKACTIVE_LSB : integer := 3;
constant C_FIELD_GT_RXCDRLOCK_MSB : integer := 4;
constant C_FIELD_GT_RXCDRLOCK_LSB : integer := 4;
constant C_FIELD_GT_TXRESETDONE_MSB : integer := 5;
constant C_FIELD_GT_TXRESETDONE_LSB : integer := 5;
constant C_FIELD_GT_RXRESETDONE_MSB : integer := 6;
constant C_FIELD_GT_RXRESETDONE_LSB : integer := 6;
constant C_FIELD_GT_RXBYTEISALIGNED_MSB : integer := 7;
constant C_FIELD_GT_RXBYTEISALIGNED_LSB : integer := 7;
constant C_FIELD_GT_RXBYTEREALIGN_MSB : integer := 8;
constant C_FIELD_GT_RXBYTEREALIGN_LSB : integer := 8;
constant C_FIELD_GT_RXCOMMADET_MSB : integer := 9;
constant C_FIELD_GT_RXCOMMADET_LSB : integer := 9;
constant C_FIELD_GT_RXCOMMADETEN_MSB : integer := 10;
constant C_FIELD_GT_RXCOMMADETEN_LSB : integer := 10;
constant C_FIELD_GT_RSTALL_MSB : integer := 11;
constant C_FIELD_GT_RSTALL_LSB : integer := 11;
constant C_FIELD_PROTOCOL_FRAMECNT_MSB : integer := 15;
constant C_FIELD_PROTOCOL_FRAMECNT_LSB : integer := 0;
constant C_FIELD_PROTOCOL_FRAMEERROR_MSB : integer := 16;
constant C_FIELD_PROTOCOL_FRAMEERROR_LSB : integer := 16;
-- registers
signal reg_sfp : std_logic_vector(32-1 downto 0);
signal reg_gt : std_logic_vector(32-1 downto 0);
signal reg_protocol : std_logic_vector(32-1 downto 0);
-- read
type t_state_read is (sReadIdle, sReadValid);
signal state_read : t_state_read;
signal rdata_reg : std_logic_vector(31 downto 0);
signal raddr_word : integer;
signal arready_wire : std_logic;
signal rvalid_wire : std_logic;
-- write
type t_state_write is (sWriteIdle, sWriteWaitData, sWriteWaitAddr, sWriteResp);
signal state_write : t_state_write;
signal state_write_prev : t_state_write;
signal waddr_reg : std_logic_vector(G_ADDR_W-1 downto 0);
signal wdata_reg : std_logic_vector(31 downto 0);
signal waddr_word : integer;
signal awready_wire : std_logic;
signal wready_wire : std_logic;
signal bvalid_wire : std_logic;
begin
reg_sfp(0) <= sfp_txfault_i when rising_edge(clk);
reg_sfp(1) <= sfp_rxlos_i when rising_edge(clk);
reg_sfp(2) <= sfp_modabs_i when rising_edge(clk);
sfp_txdisable_o <= reg_sfp(3);
reg_gt(0) <= gt_powergood_i when rising_edge(clk);
reg_gt(1) <= gt_qplllock_i when rising_edge(clk);
reg_gt(2) <= gt_txclkactive_i when rising_edge(clk);
reg_gt(3) <= gt_rxclkactive_i when rising_edge(clk);
reg_gt(4) <= gt_rxcdrlock_i when rising_edge(clk);
reg_gt(5) <= gt_txresetdone_i when rising_edge(clk);
reg_gt(6) <= gt_rxresetdone_i when rising_edge(clk);
reg_gt(7) <= gt_rxbyteisaligned_i when rising_edge(clk);
reg_gt(8) <= gt_rxbyterealign_i when rising_edge(clk);
reg_gt(9) <= gt_rxcommadet_i when rising_edge(clk);
gt_rxcommadeten_o <= reg_gt(10);
gt_rstall_o <= reg_gt(11);
reg_protocol(15 downto 0) <= protocol_framecnt_i when rising_edge(clk);
reg_protocol(16) <= protocol_frameerror_i when rising_edge(clk);
proc_state_read: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state_read <= sReadIdle;
else
case state_read is
when sReadIdle =>
if S_AXI_ARVALID = '1' then
state_read <= sReadValid;
end if;
when sReadValid =>
if S_AXI_RREADY = '1' then
state_read <= sReadIdle;
end if;
end case;
end if;
end if;
end process;
raddr_word <= to_integer(unsigned(S_AXI_ARADDR(G_ADDR_W-1 downto 2)));
-- ### read logic
proc_rdata_reg: process (clk)
begin
if rising_edge(clk) then
rdata_reg <= (others => '0');
case raddr_word is
when C_ADDR_SFP =>
rdata_reg(0 downto 0) <= reg_sfp(0 downto 0);
rdata_reg(1 downto 1) <= reg_sfp(1 downto 1);
rdata_reg(2 downto 2) <= reg_sfp(2 downto 2);
rdata_reg(3 downto 3) <= reg_sfp(3 downto 3);
when C_ADDR_GT =>
rdata_reg(0 downto 0) <= reg_gt(0 downto 0);
rdata_reg(1 downto 1) <= reg_gt(1 downto 1);
rdata_reg(2 downto 2) <= reg_gt(2 downto 2);
rdata_reg(3 downto 3) <= reg_gt(3 downto 3);
rdata_reg(4 downto 4) <= reg_gt(4 downto 4);
rdata_reg(5 downto 5) <= reg_gt(5 downto 5);
rdata_reg(6 downto 6) <= reg_gt(6 downto 6);
rdata_reg(7 downto 7) <= reg_gt(7 downto 7);
rdata_reg(8 downto 8) <= reg_gt(8 downto 8);
rdata_reg(9 downto 9) <= reg_gt(9 downto 9);
rdata_reg(10 downto 10) <= reg_gt(10 downto 10);
rdata_reg(11 downto 11) <= reg_gt(11 downto 11);
when C_ADDR_PROTOCOL =>
rdata_reg(15 downto 0) <= reg_protocol(15 downto 0);
rdata_reg(16 downto 16) <= reg_protocol(16 downto 16);
when others =>
-- decode error
rdata_reg <= x"badc0fee";
end case;
end if;
end process;
proc_read_output: process (state_read)
begin
case state_read is
when sReadIdle =>
arready_wire <= '1';
rvalid_wire <= '0';
when sReadValid =>
arready_wire <= '0';
rvalid_wire <= '1';
when others =>
arready_wire <= '0';
rvalid_wire <= '0';
end case;
end process;
S_AXI_ARREADY <= arready_wire;
S_AXI_RVALID <= rvalid_wire;
S_AXI_RDATA <= rdata_reg;
S_AXI_RRESP <= "00";
proc_state_write_prev: process (clk) begin
if rising_edge(clk) then
state_write_prev <= state_write;
end if;
end process;
proc_state_write: process (clk) begin
if rising_edge (clk) then
if reset = '1' then
state_write <= sWriteIdle;
else
case state_write is
when sWriteIdle =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
wdata_reg <= S_AXI_WDATA;
elsif S_AXI_AWVALID = '1' and S_AXI_WVALID = '0' then
state_write <= sWriteWaitData;
waddr_reg <= S_AXI_AWADDR;
elsif S_AXI_AWVALID = '0' and S_AXI_WVALID = '1' then
state_write <= sWriteWaitAddr;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitData =>
if S_AXI_WVALID = '1' then
state_write <= sWriteResp;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitAddr =>
if S_AXI_AWVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
end if;
when sWriteResp =>
if S_AXI_BREADY = '1' then
state_write <= sWriteIdle;
end if;
end case;
end if;
end if;
end process;
waddr_word <= to_integer(unsigned(waddr_reg(G_ADDR_W-1 downto 2)));
-- ### write logic (use waddr_word and wdata_reg)
proc_write: process (clk) begin
if rising_edge(clk) then
if reset = '1' then
reg_sfp(3 downto 3) <= "0";
reg_gt(10 downto 10) <= "1";
reg_gt(11 downto 11) <= "1";
else
-- default (pulse)
-- default (swmod)
-- default (woclr)
if state_write = sWriteResp and state_write_prev /= sWriteResp then
case waddr_word is
when C_ADDR_SFP =>
reg_sfp(3 downto 3) <= wdata_reg(3 downto 3);
when C_ADDR_GT =>
reg_gt(10 downto 10) <= wdata_reg(10 downto 10);
reg_gt(11 downto 11) <= wdata_reg(11 downto 11);
when C_ADDR_PROTOCOL =>
null;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
proc_write_output: process (state_write) begin
case state_write is
when sWriteIdle =>
awready_wire <= '1';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitData =>
awready_wire <= '0';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitAddr =>
awready_wire <= '1';
wready_wire <= '0';
bvalid_wire <= '0';
when sWriteResp =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '1';
when others =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '0';
end case;
end process;
S_AXI_AWREADY <= awready_wire;
S_AXI_WREADY <= wready_wire;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= bvalid_wire;
end architecture;
hdl/top_combpm_electron.vhd
+ 70
− 63
View file @ 5084a443
......@@ -8,9 +8,9 @@ use ieee.numeric_std.all;
entity top_combpm_electron is
port(
clk_gt : out std_logic; -- Clock ref from GT
rst_n : in std_logic;
clk_100 : in std_logic; -- Freerunning clock for GT
gt_clk : out std_logic; -- Data clock from GT
rst_n : in std_logic; -- Asyncheonous reset
free_100_clk : in std_logic; -- Freerunning clock for GT
-- Differential reference clock inputs and buffered output
mgtrefclk_p : in std_logic;
......@@ -28,36 +28,36 @@ entity top_combpm_electron is
sfp_tx_fault : in std_logic;
-- AXIS interface
m_axi_tid : out std_logic_vector(0 downto 0);
m_axi_tdest : out std_logic_vector(9 downto 0);
m_axi_tdata : out std_logic_vector(127 downto 0);
m_axi_tstrb : out std_logic_vector(15 downto 0);
m_axi_tkeep : out std_logic_vector(15 downto 0);
m_axi_tlast : out std_logic;
m_axi_tuser : out std_logic_vector(0 downto 0);
m_axi_tvalid : out std_logic;
m_axi_tready : in std_logic;
m_axis_tid : out std_logic_vector(0 downto 0);
m_axis_tdest : out std_logic_vector(9 downto 0);
m_axis_tdata : out std_logic_vector(127 downto 0);
m_axis_tstrb : out std_logic_vector(15 downto 0);
m_axis_tkeep : out std_logic_vector(15 downto 0);
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic_vector(0 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
-- AXI bus interface
S_AXI_AWADDR : in std_logic_vector(7 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(7 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
s_axi_awaddr : in std_logic_vector(7 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(32-1 downto 0);
s_axi_wstrb : in std_logic_vector(32/8-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(7 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(32-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end top_combpm_electron;
......@@ -69,22 +69,19 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of m_axi_tid : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tdest : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TDEST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TDATA";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tstrb : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TSTRB";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tkeep : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TKEEP";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tlast : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TLAST";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tuser : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TUSER";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tready : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TREADY";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
ATTRIBUTE X_INTERFACE_PARAMETER of gt_clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi, ASSOCIATED_RESET rst_n";
--ATTRIBUTE X_INTERFACE_INFO of free_100_clk : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
------------------------
-- SIGNAL DECLARATION --
------------------------
signal sync_rst : std_logic; -- Reset synchonized to clock
signal rst : std_logic;
signal tx_disable : std_logic;
signal rx_commadeten : std_logic;
......@@ -113,6 +110,16 @@ architecture struct of top_combpm_electron is
begin
---------------------------
-- RESET SYNCHRONIZATION --
---------------------------
inst_cdc_arst: xpm_cdc_async_rst
port map(
src_arst => rst,
dest_clk => gt_clk,
dest_arst => sync_rst
);
-- Reset invert polarity
rst <= not rst_n;
......@@ -144,7 +151,7 @@ begin
protocol_frameerror_i => frame_error,
clk => gt_usrclk,
reset => rst,
reset => sync_rst,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
......@@ -192,15 +199,15 @@ begin
gt_rxcommadeten => gt_rxcommadeten,
gt_txdisable => gt_txdisable,
m_axi_tid => m_axi_tid,
m_axi_tdest => m_axi_tdest,
m_axi_tdata => m_axi_tdata,
m_axi_tstrb => m_axi_tstrb,
m_axi_tkeep => m_axi_tkeep,
m_axi_tlast => m_axi_tlast,
m_axi_tuser => m_axi_tuser,
m_axi_tvalid => m_axi_tvalid,
m_axi_tready => m_axi_tready,
m_axi_tid => m_axis_tid,
m_axi_tdest => m_axis_tdest,
m_axi_tdata => m_axis_tdata,
m_axi_tstrb => m_axis_tstrb,
m_axi_tkeep => m_axis_tkeep,
m_axi_tlast => m_axis_tlast,
m_axi_tuser => m_axis_tuser,
m_axi_tvalid => m_axis_tvalid,
m_axi_tready => m_axis_tready,
tx_disable_i => tx_disable,
rx_commadeten_i => rx_commadeten,
......@@ -213,7 +220,7 @@ begin
----------------
-- GT WRAPPER --
----------------
clk_gt <= gt_userclk;
gt_clk <= gt_userclk;
inst_gtwrapper: entity work.combpm_gtwrapper
port map(
-- 100MHz clock, main ref clock
......
tcl/combpm.tcl
+ 2
− 7
View file @ 5084a443
......@@ -8,13 +8,8 @@ set_property top ${top} [current_fileset]
# Compilation order in auto
set_property source_mgmt_mode All ${ip_project}
# Read source files
read_vhdl "hdl/top_combpm_electron.vhd"
read_vhdl "hdl/combpm_protocol_electron.vhd"
read_vhdl "hdl/combpm_protocol_electron_ctrl.vhd"
read_vhdl "hdl/combpm_gtwrapper.vhd"
read_vhdl "hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd"
import_ip -name combpm_gtwrapper "ip_cores/CAENELSSFP_1L.xci"
# Read sources
source tcl/sources.tcl
update_compile_order -fileset sources_1
# Package project
......
tcl/metadata.tcl
+ 8
− 8
View file @ 5084a443
......@@ -5,16 +5,16 @@ set part "xczu11eg-ffvc1760-2L-e"
set ip_properties [ list \
vendor "synchrotron-soleil.fr" \
library "fofb" \
library "user" \
name ${design} \
version "1.0" \
taxonomy "/transceiver" \
display_name "Electron Communication Decoder" \
description "Decode CC protocol from a transceiver interface and generate AXIS frames" \
taxonomy "/Communication_&_Networking/Serial_Interfaces" \
display_name "BPM Communication Decoder" \
description "Decode CC protocol (Electron) from a transceiver interface and generate AXIS frames" \
vendor_display_name "Synchrotron SOLEIL" \
company_url "" \
company_url "http://www.synchrotron-soleil.fr" \
]
set family_lifecycle { \
zynquplus Beta \
}
set family_lifecycle [list \
zynquplus{${part}} Beta \
]
ip_cores/CAENELSSFP_1L.xci → xci/CAENELS4SFP_1L.xci
+ 0
− 0
View file @ 5084a443
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