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Commit dda4d426 authored by BRONES Romain's avatar BRONES Romain
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Modify the configuration of the GT wizard wrapper 

* Use a package
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library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity combpm_gtsfp_caenelsfmc4sfp is
port(
-- 100MHz clock, main ref clock
clk_100 : in std_logic;
-- User clock provided by GT
usrclk : out std_logic;
-- Async reset active low
rst_n : in std_logic;
-- Differential reference clock inputs
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
-- SFP01 interface
sfp01_txn : out std_logic;
sfp01_rxn : in std_logic;
sfp01_txp : out std_logic;
sfp01_rxp : in std_logic;
sfp01_rx_los : in std_logic;
sfp01_mod_abs : in std_logic;
sfp01_tx_disable : out std_logic;
sfp01_tx_fault : in std_logic;
-- GT01 interface
gt01_datarx : out std_logic_vector(15 downto 0);
gt01_datatx : in std_logic_vector(15 downto 0);
gt01_powergood : out std_logic;
gt01_qplllock : out std_logic;
gt01_txclkactive : out std_logic;
gt01_rxclkactive : out std_logic;
gt01_txresetdone : out std_logic;
gt01_rxresetdone : out std_logic;
gt01_rxcdrlock : out std_logic;
gt01_rxbyteisaligned : out std_logic;
gt01_rxbyterealign : out std_logic;
gt01_rxcommadet : out std_logic;
gt01_txfault : out std_logic;
gt01_rxlos : out std_logic;
gt01_modabs : out std_logic;
gt01_rstall : in std_logic;
gt01_rxcommadeten : in std_logic;
gt01_txdisable : in std_logic;
-- SFP02 interface
sfp02_txn : out std_logic;
sfp02_rxn : in std_logic;
sfp02_txp : out std_logic;
sfp02_rxp : in std_logic;
sfp02_rx_los : in std_logic;
sfp02_mod_abs : in std_logic;
sfp02_tx_disable : out std_logic;
sfp02_tx_fault : in std_logic;
-- GT02 interface
gt02_datarx : out std_logic_vector(15 downto 0);
gt02_datatx : in std_logic_vector(15 downto 0);
gt02_powergood : out std_logic;
gt02_qplllock : out std_logic;
gt02_txclkactive : out std_logic;
gt02_rxclkactive : out std_logic;
gt02_txresetdone : out std_logic;
gt02_rxresetdone : out std_logic;
gt02_rxcdrlock : out std_logic;
gt02_rxbyteisaligned : out std_logic;
gt02_rxbyterealign : out std_logic;
gt02_rxcommadet : out std_logic;
gt02_txfault : out std_logic;
gt02_rxlos : out std_logic;
gt02_modabs : out std_logic;
gt02_rstall : in std_logic;
gt02_rxcommadeten : in std_logic;
gt02_txdisable : in std_logic;
-- SFP03 interface
sfp03_txn : out std_logic;
sfp03_rxn : in std_logic;
sfp03_txp : out std_logic;
sfp03_rxp : in std_logic;
sfp03_rx_los : in std_logic;
sfp03_mod_abs : in std_logic;
sfp03_tx_disable : out std_logic;
sfp03_tx_fault : in std_logic;
-- GT03 interface
gt03_datarx : out std_logic_vector(15 downto 0);
gt03_datatx : in std_logic_vector(15 downto 0);
gt03_powergood : out std_logic;
gt03_qplllock : out std_logic;
gt03_txclkactive : out std_logic;
gt03_rxclkactive : out std_logic;
gt03_txresetdone : out std_logic;
gt03_rxresetdone : out std_logic;
gt03_rxcdrlock : out std_logic;
gt03_rxbyteisaligned : out std_logic;
gt03_rxbyterealign : out std_logic;
gt03_rxcommadet : out std_logic;
gt03_txfault : out std_logic;
gt03_rxlos : out std_logic;
gt03_modabs : out std_logic;
gt03_rstall : in std_logic;
gt03_rxcommadeten : in std_logic;
gt03_txdisable : in std_logic;
-- SFP04 interface
sfp04_txn : out std_logic;
sfp04_rxn : in std_logic;
sfp04_txp : out std_logic;
sfp04_rxp : in std_logic;
sfp04_rx_los : in std_logic;
sfp04_mod_abs : in std_logic;
sfp04_tx_disable : out std_logic;
sfp04_tx_fault : in std_logic;
-- GT04 interface
gt04_datarx : out std_logic_vector(15 downto 0);
gt04_datatx : in std_logic_vector(15 downto 0);
gt04_powergood : out std_logic;
gt04_qplllock : out std_logic;
gt04_txclkactive : out std_logic;
gt04_rxclkactive : out std_logic;
gt04_txresetdone : out std_logic;
gt04_rxresetdone : out std_logic;
gt04_rxcdrlock : out std_logic;
gt04_rxbyteisaligned : out std_logic;
gt04_rxbyterealign : out std_logic;
gt04_rxcommadet : out std_logic;
gt04_txfault : out std_logic;
gt04_rxlos : out std_logic;
gt04_modabs : out std_logic;
gt04_rstall : in std_logic;
gt04_rxcommadeten : in std_logic;
gt04_txdisable : in std_logic
);
end combpm_gtsfp_caenelsfmc4sfp;
architecture rtl of combpm_gtsfp_caenelsfmc4sfp is
--------------------------------
-- INTERFACE PORT ASSOCIATION --
--------------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO of sfp01_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp01_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp01_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp01_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp01_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt01_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt01_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt01_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT01 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt01_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt01_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt01_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt01_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT01 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt01_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt01_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp02_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp02_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp02_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp02_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp02_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt02_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt02_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt02_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT02 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt02_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt02_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt02_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt02_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT02 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt02_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt02_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp03_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp03_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp03_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp03_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp03_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt03_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt03_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt03_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT03 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt03_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt03_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt03_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt03_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT03 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt03_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt03_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp04_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp04_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp04_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp04_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp04_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt04_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt04_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt04_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT04 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt04_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt04_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt04_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt04_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT04 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt04_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt04_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txdisable";
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT gtwizard_ultrascale_caenelsfmc4sfp
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal txclkactive : std_logic;
signal rxclkactive : std_logic;
signal rstall : std_logic;
signal txresetdone : std_logic;
signal rxresetdone : std_logic;
signal qplllock : std_logic;
signal ref_clk : std_logic;
begin
---------------------
-- DIFF CLK BUFFER --
---------------------
ibufd_clkref_inst: IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => ref_clk,
ODIV2 => open,
CEB => '0',
I => mgtrefclk_p,
IB => mgtrefclk_n
);
--------------------
-- GLOBAL SIGNALS --
--------------------
gt01_txclkactive <= txclkactive;
gt02_txclkactive <= txclkactive;
gt03_txclkactive <= txclkactive;
gt04_txclkactive <= txclkactive;
gt01_rxclkactive <= rxclkactive;
gt02_rxclkactive <= rxclkactive;
gt03_rxclkactive <= rxclkactive;
gt04_rxclkactive <= rxclkactive;
rstall <= gt01_rstall
or gt02_rstall
or gt03_rstall
or gt04_rstall;
gt01_txresetdone <= txresetdone;
gt02_txresetdone <= txresetdone;
gt03_txresetdone <= txresetdone;
gt04_txresetdone <= txresetdone;
gt01_rxresetdone <= rxresetdone;
gt02_rxresetdone <= rxresetdone;
gt03_rxresetdone <= rxresetdone;
gt04_rxresetdone <= rxresetdone;
gt01_qplllock <= qplllock;
gt02_qplllock <= qplllock;
gt03_qplllock <= qplllock;
gt04_qplllock <= qplllock;
--------------------------
-- TRANSCEIVER INSTANCE --
--------------------------
gtwiz_inst: gtwizard_ultrascale_caenelsfmc4sfp
PORT MAP (
gtwiz_userclk_tx_reset_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open,
gtwiz_userclk_tx_active_out(0) => txclkactive,
gtwiz_userclk_rx_reset_in => "0",
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userclk_rx_usrclk2_out => open,
gtwiz_userclk_rx_active_out(0) => rxclkactive,
gtwiz_reset_clk_freerun_in(0) => clk_100,
gtwiz_reset_all_in(0) => rstall,
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
gtwiz_reset_rx_datapath_in => "0",
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out(0) => txresetdone,
gtwiz_reset_rx_done_out(0) => rxresetdone,
gtwiz_userdata_tx_in(15 downto 0) => gt03_datatx,
gtwiz_userdata_tx_in(31 downto 16) => gt02_datatx,
gtwiz_userdata_tx_in(47 downto 32) => gt04_datatx,
gtwiz_userdata_tx_in(63 downto 48) => gt01_datatx,
gtwiz_userdata_rx_out(15 downto 0) => gt03_datarx,
gtwiz_userdata_rx_out(31 downto 16) => gt02_datarx,
gtwiz_userdata_rx_out(47 downto 32) => gt04_datarx,
gtwiz_userdata_rx_out(63 downto 48) => gt01_datarx,
gtrefclk01_in(0) => ref_clk,
qpll1lock_out(0) => qplllock,
qpll1outclk_out => open,
qpll1outrefclk_out => open,
gthrxn_in(0) => sfp03_rxn,
gthrxn_in(1) => sfp02_rxn,
gthrxn_in(2) => sfp04_rxn,
gthrxn_in(3) => sfp01_rxn,
gthrxp_in(0) => sfp03_rxp,
gthrxp_in(1) => sfp02_rxp,
gthrxp_in(2) => sfp04_rxp,
gthrxp_in(3) => sfp01_rxp,
rxbufreset_in => (others => '0'),
rx8b10ben_in => (others => '1'),
rxcommadeten_in(0) => gt03_rxcommadeten,
rxcommadeten_in(1) => gt02_rxcommadeten,
rxcommadeten_in(2) => gt04_rxcommadeten,
rxcommadeten_in(3) => gt01_rxcommadeten,
rxmcommaalignen_in => (others => '1'),
rxpcommaalignen_in => (others => '1'),
tx8b10ben_in => (others => '1'),
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gthtxn_out(0) => sfp03_txn,
gthtxn_out(1) => sfp02_txn,
gthtxn_out(2) => sfp04_txn,
gthtxn_out(3) => sfp01_txn,
gthtxp_out(0) => sfp03_txp,
gthtxp_out(1) => sfp02_txp,
gthtxp_out(2) => sfp04_txp,
gthtxp_out(3) => sfp01_txp,
gtpowergood_out(0) => gt03_powergood,
gtpowergood_out(1) => gt02_powergood,
gtpowergood_out(2) => gt04_powergood,
gtpowergood_out(3) => gt01_powergood,
rxbufstatus_out => open,
rxbyteisaligned_out(0) => gt03_rxbyteisaligned,
rxbyteisaligned_out(1) => gt02_rxbyteisaligned,
rxbyteisaligned_out(2) => gt04_rxbyteisaligned,
rxbyteisaligned_out(3) => gt01_rxbyteisaligned,
rxbyterealign_out(0) => gt03_rxbyterealign,
rxbyterealign_out(1) => gt02_rxbyterealign,
rxbyterealign_out(2) => gt04_rxbyterealign,
rxbyterealign_out(3) => gt01_rxbyterealign,
rxcdrlock_out(0) => gt03_rxcdrlock,
rxcdrlock_out(1) => gt02_rxcdrlock,
rxcdrlock_out(2) => gt04_rxcdrlock,
rxcdrlock_out(3) => gt01_rxcdrlock,
rxclkcorcnt_out => open,
rxcommadet_out(0) => gt03_rxcommadet,
rxcommadet_out(1) => gt02_rxcommadet,
rxcommadet_out(2) => gt04_rxcommadet,
rxcommadet_out(3) => gt01_rxcommadet,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open
);
----------------------
-- DIRECT CONNEXION --
----------------------
gt01_txfault <= sfp01_tx_fault;
gt02_txfault <= sfp02_tx_fault;
gt03_txfault <= sfp03_tx_fault;
gt04_txfault <= sfp04_tx_fault;
gt01_rxlos <= sfp01_rx_los;
gt02_rxlos <= sfp02_rx_los;
gt03_rxlos <= sfp03_rx_los;
gt04_rxlos <= sfp04_rx_los;
gt01_modabs <= sfp01_mod_abs;
gt02_modabs <= sfp02_mod_abs;
gt03_modabs <= sfp03_mod_abs;
gt04_modabs <= sfp04_mod_abs;
sfp01_tx_disable <= gt01_txdisable;
sfp02_tx_disable <= gt02_txdisable;
sfp03_tx_disable <= gt03_txdisable;
sfp04_tx_disable <= gt04_txdisable;
end architecture rtl;
hdl/combpm_gtsfp_htgfmc2qsfp.vhd deleted 100644 → 0
+ 0
− 688
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This diff is collapsed.
hdl/combpm_gtwrapper.vhd 0 → 100644
+ 181
− 0
View file @ dda4d426
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity combpm_gtwrapper is
port(
-- 100MHz clock, main ref clock
clk_100 : in std_logic;
-- Usrclock for data transfer
usrclk : out std_logic;
-- Async reset active low
rst_n : in std_logic;
-- Differential reference clock inputs and buffered output
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
mgtrefclk : out std_logic;
-- SFP interfaces
sfp_txp : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_txn : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rxp : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rxn : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rx_los : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_mod_abs : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_tx_disable : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_tx_fault : in std_logic_vector(C_NUM_CHAN-1 downto 0);
-- GT interfaces
gt_datarx : out std_logic_vector(16*C_NUM_CHAN-1 downto 0);
gt_datatx : in std_logic_vector(16*C_NUM_CHAN-1 downto 0);
gt_powergood : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_qplllock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcdrlock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxbyteisaligned : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxbyterealign : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcommadet : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txfault : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxlos : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_modabs : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rstall : in std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcommadeten : in std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txdisable : in std_logic_vector(C_NUM_CHAN-1 downto 0)
);
end entity combpm_gtwrapper;
architecture struct of combpm_gtwrapper is
--------------------------------
-- INTERFACE PORT ASSOCIATION --
--------------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
------------------------
-- SIGNAL DECLARATION --
------------------------
signal txclkactive : std_logic;
signal rxclkactive : std_logic;
signal rstall : std_logic;
signal txresetdone : std_logic;
signal rxresetdone : std_logic;
signal qplllock : std_logic;
signal ref_clk : std_logic;
begin
---------------------
-- DIFF CLK BUFFER --
---------------------
ibufd_clkref_inst: IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => ref_clk,
ODIV2 => open,
CEB => '0',
I => mgtrefclk_p,
IB => mgtrefclk_n
);
-- Connect to output port
mgtrefclk <= ref_clk;
-----------------
-- MAP SIGNALS --
-----------------
g_map_sigs:for I in 0 to C_NUM_CHAN generate
gt_txclkactive(I) <= txclkactive;
gt_rxclkactive(I) <= rxclkactive;
gt_txresetdone(I) <= txresetdone;
gt_rxresetdone(I) <= rxresetdone;
gt_qplllock(I) <= qplllock;
end generate g_glob_sigs;
rstall <= or_reduce(gt_rstall);
gt_txfault <= sfp_tx_fault;
gt_rxlos <= sfp_rx_los;
gt_modabs <= sfp_mod_abs;
sfp_tx_disable <= gt_txdisable;
--------------------------
-- TRANSCEIVER INSTANCE --
--------------------------
gtwiz_inst: combpm_gtwizard
PORT MAP (
gtwiz_userclk_tx_reset_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open,
gtwiz_userclk_tx_active_out(0) => txclkactive,
gtwiz_userclk_rx_reset_in => "0",
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userclk_rx_usrclk2_out => open,
gtwiz_userclk_rx_active_out(0) => rxclkactive,
gtwiz_reset_clk_freerun_in(0) => clk_100,
gtwiz_reset_all_in(0) => rstall,
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
gtwiz_reset_rx_datapath_in => "0",
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out(0) => txresetdone,
gtwiz_reset_rx_done_out(0) => rxresetdone,
gtwiz_userdata_tx_in => gt_datatx,
gtwiz_userdata_rx_out => gt_datarx,
gtrefclk01_in(0) => ref_clk,
qpll1lock_out(0) => qplllock,
qpll1outclk_out => open,
qpll1outrefclk_out => open,
gthrxn_in => sfp_rxn,
gthrxp_in => sfp_rxp,
rxbufreset_in => (others => '0'),
rx8b10ben_in => (others => '1'),
rxcommadeten_in => gt_rxcommadeten,
rxmcommaalignen_in => (others => '1'),
rxpcommaalignen_in => (others => '1'),
tx8b10ben_in => (others => '1'),
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gthtxn_out => sfp_txn,
gthtxp_out => sfp_txp,
gtpowergood_out => gt_powergood,
rxbufstatus_out => open,
rxbyteisaligned_out => gt_rxbyteisaligned,
rxbyterealign_out => gt_rxbyterealign,
rxcdrlock_out => gt_rxcdrlock,
rxclkcorcnt_out => open,
rxcommadet_out => gt_rxcommadet,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open
);
end architecture struct;
hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd 0 → 100644
+ 59
− 0
View file @ dda4d426
package combpm_gtwrapper_pkg is
constant C_NUM_CHAN = 1;
COMPONENT gtwizard_ultrascale_caenelsfmc4sfp
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
end combpm_gtwrapper_pkg;
hdl/combpm_htg2qsfp_fmc1_4L_L.vhd deleted 100644 → 0
+ 0
− 477
View file @ b9ec9d8c
This diff is collapsed.
ip_cores/HTG2QSFP_FMC1_4L_L.xci deleted 100644 → 0
+ 0
− 1425
View file @ b9ec9d8c
This diff is collapsed.
ip_cores/gtwizard_ultrascale_htgfmc2qsfp.xci deleted 100644 → 0
+ 0
− 1427
View file @ b9ec9d8c
This diff is collapsed.
scripts/add_files.tcl
+ 4
− 2
View file @ dda4d426
......@@ -2,9 +2,11 @@
set module_root [file normalize [file dirname [file normalize [info script]]]/../]
add_files "$module_root/hdl/combpm_protocol_electron_ctrl.vhd"
add_files "$module_root/hdl/combpm_protocol_electron.vhd"
add_files "$module_root/hdl/combpm_gtsfp_htgfmc2qsfp.vhd"
add_files "$module_root/hdl/combpm_gtwrapper.vhd"
add_files "$module_root/hdl/top_combpm_electron.vhd"
import_ip "$module_root/ip_cores/gtwizard_ultrascale_htgfmc2qsfp.xci"
add_files "$module_root/hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd"
import_ip "$module_root/ip_cores/CAENELSSFP_1L.xci"
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