* Use a package

* HTG2QSFP, on FMC1, Only 4 lanes

Calling this script will add VHDL and XCI source files to the current
project.

* Change the testbench interface
* Add a very simple script to compile and bring up GUI

* Wrap the protocol bloc and the aximm control in a structural top
  level.
* Get rid of the CDC, use only one clock. Domain crossing will be
  outside this bloc.

* Import sources from Cell Node initial project