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Commit ea910ec4 authored by BRONES Romain's avatar BRONES Romain
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* Import sources from Cell Node initial project
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library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity combpm_gtsfp_caenelsfmc4sfp is
port(
-- 100MHz clock, main ref clock
clk_100 : in std_logic;
-- User clock provided by GT
usrclk : out std_logic;
-- Async reset active low
rst_n : in std_logic;
-- Differential reference clock inputs
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
-- SFP01 interface
sfp01_txn : out std_logic;
sfp01_rxn : in std_logic;
sfp01_txp : out std_logic;
sfp01_rxp : in std_logic;
sfp01_rx_los : in std_logic;
sfp01_mod_abs : in std_logic;
sfp01_tx_disable : out std_logic;
sfp01_tx_fault : in std_logic;
-- GT01 interface
gt01_datarx : out std_logic_vector(15 downto 0);
gt01_datatx : in std_logic_vector(15 downto 0);
gt01_powergood : out std_logic;
gt01_qplllock : out std_logic;
gt01_txclkactive : out std_logic;
gt01_rxclkactive : out std_logic;
gt01_txresetdone : out std_logic;
gt01_rxresetdone : out std_logic;
gt01_rxcdrlock : out std_logic;
gt01_rxbyteisaligned : out std_logic;
gt01_rxbyterealign : out std_logic;
gt01_rxcommadet : out std_logic;
gt01_txfault : out std_logic;
gt01_rxlos : out std_logic;
gt01_modabs : out std_logic;
gt01_rstall : in std_logic;
gt01_rxcommadeten : in std_logic;
gt01_txdisable : in std_logic;
-- SFP02 interface
sfp02_txn : out std_logic;
sfp02_rxn : in std_logic;
sfp02_txp : out std_logic;
sfp02_rxp : in std_logic;
sfp02_rx_los : in std_logic;
sfp02_mod_abs : in std_logic;
sfp02_tx_disable : out std_logic;
sfp02_tx_fault : in std_logic;
-- GT02 interface
gt02_datarx : out std_logic_vector(15 downto 0);
gt02_datatx : in std_logic_vector(15 downto 0);
gt02_powergood : out std_logic;
gt02_qplllock : out std_logic;
gt02_txclkactive : out std_logic;
gt02_rxclkactive : out std_logic;
gt02_txresetdone : out std_logic;
gt02_rxresetdone : out std_logic;
gt02_rxcdrlock : out std_logic;
gt02_rxbyteisaligned : out std_logic;
gt02_rxbyterealign : out std_logic;
gt02_rxcommadet : out std_logic;
gt02_txfault : out std_logic;
gt02_rxlos : out std_logic;
gt02_modabs : out std_logic;
gt02_rstall : in std_logic;
gt02_rxcommadeten : in std_logic;
gt02_txdisable : in std_logic;
-- SFP03 interface
sfp03_txn : out std_logic;
sfp03_rxn : in std_logic;
sfp03_txp : out std_logic;
sfp03_rxp : in std_logic;
sfp03_rx_los : in std_logic;
sfp03_mod_abs : in std_logic;
sfp03_tx_disable : out std_logic;
sfp03_tx_fault : in std_logic;
-- GT03 interface
gt03_datarx : out std_logic_vector(15 downto 0);
gt03_datatx : in std_logic_vector(15 downto 0);
gt03_powergood : out std_logic;
gt03_qplllock : out std_logic;
gt03_txclkactive : out std_logic;
gt03_rxclkactive : out std_logic;
gt03_txresetdone : out std_logic;
gt03_rxresetdone : out std_logic;
gt03_rxcdrlock : out std_logic;
gt03_rxbyteisaligned : out std_logic;
gt03_rxbyterealign : out std_logic;
gt03_rxcommadet : out std_logic;
gt03_txfault : out std_logic;
gt03_rxlos : out std_logic;
gt03_modabs : out std_logic;
gt03_rstall : in std_logic;
gt03_rxcommadeten : in std_logic;
gt03_txdisable : in std_logic;
-- SFP04 interface
sfp04_txn : out std_logic;
sfp04_rxn : in std_logic;
sfp04_txp : out std_logic;
sfp04_rxp : in std_logic;
sfp04_rx_los : in std_logic;
sfp04_mod_abs : in std_logic;
sfp04_tx_disable : out std_logic;
sfp04_tx_fault : in std_logic;
-- GT04 interface
gt04_datarx : out std_logic_vector(15 downto 0);
gt04_datatx : in std_logic_vector(15 downto 0);
gt04_powergood : out std_logic;
gt04_qplllock : out std_logic;
gt04_txclkactive : out std_logic;
gt04_rxclkactive : out std_logic;
gt04_txresetdone : out std_logic;
gt04_rxresetdone : out std_logic;
gt04_rxcdrlock : out std_logic;
gt04_rxbyteisaligned : out std_logic;
gt04_rxbyterealign : out std_logic;
gt04_rxcommadet : out std_logic;
gt04_txfault : out std_logic;
gt04_rxlos : out std_logic;
gt04_modabs : out std_logic;
gt04_rstall : in std_logic;
gt04_rxcommadeten : in std_logic;
gt04_txdisable : in std_logic
);
end combpm_gtsfp_caenelsfmc4sfp;
architecture rtl of combpm_gtsfp_caenelsfmc4sfp is
--------------------------------
-- INTERFACE PORT ASSOCIATION --
--------------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO of sfp01_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp01_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp01_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp01_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp01_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp01_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP01 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt01_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt01_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt01_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT01 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt01_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt01_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt01_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt01_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT01 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt01_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt01_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp02_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp02_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp02_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp02_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp02_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp02_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP02 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt02_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt02_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt02_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT02 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt02_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt02_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt02_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt02_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT02 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt02_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt02_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp03_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp03_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp03_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp03_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp03_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp03_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP03 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt03_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt03_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt03_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT03 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt03_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt03_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt03_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt03_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT03 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt03_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt03_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txdisable";
ATTRIBUTE X_INTERFACE_INFO of sfp04_txn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rxn : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp04_txp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rxp : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp04_rx_los : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp04_mod_abs : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp04_tx_disable : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp04_tx_fault : SIGNAL is "xilinx.com:interface:sfp:1.0 SFP04 TX_FAULT";
ATTRIBUTE X_INTERFACE_INFO of gt04_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt04_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt04_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT04 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt04_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt04_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt04_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt04_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT04 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt04_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt04_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txdisable";
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT gtwizard_ultrascale_caenelsfmc4sfp
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcdrlock_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal txclkactive : std_logic;
signal rxclkactive : std_logic;
signal rstall : std_logic;
signal txresetdone : std_logic;
signal rxresetdone : std_logic;
signal qplllock : std_logic;
signal ref_clk : std_logic;
begin
---------------------
-- DIFF CLK BUFFER --
---------------------
ibufd_clkref_inst: IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => ref_clk,
ODIV2 => open,
CEB => '0',
I => mgtrefclk_p,
IB => mgtrefclk_n
);
--------------------
-- GLOBAL SIGNALS --
--------------------
gt01_txclkactive <= txclkactive;
gt02_txclkactive <= txclkactive;
gt03_txclkactive <= txclkactive;
gt04_txclkactive <= txclkactive;
gt01_rxclkactive <= rxclkactive;
gt02_rxclkactive <= rxclkactive;
gt03_rxclkactive <= rxclkactive;
gt04_rxclkactive <= rxclkactive;
rstall <= gt01_rstall
or gt02_rstall
or gt03_rstall
or gt04_rstall;
gt01_txresetdone <= txresetdone;
gt02_txresetdone <= txresetdone;
gt03_txresetdone <= txresetdone;
gt04_txresetdone <= txresetdone;
gt01_rxresetdone <= rxresetdone;
gt02_rxresetdone <= rxresetdone;
gt03_rxresetdone <= rxresetdone;
gt04_rxresetdone <= rxresetdone;
gt01_qplllock <= qplllock;
gt02_qplllock <= qplllock;
gt03_qplllock <= qplllock;
gt04_qplllock <= qplllock;
--------------------------
-- TRANSCEIVER INSTANCE --
--------------------------
gtwiz_inst: gtwizard_ultrascale_caenelsfmc4sfp
PORT MAP (
gtwiz_userclk_tx_reset_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open,
gtwiz_userclk_tx_active_out(0) => txclkactive,
gtwiz_userclk_rx_reset_in => "0",
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userclk_rx_usrclk2_out => open,
gtwiz_userclk_rx_active_out(0) => rxclkactive,
gtwiz_reset_clk_freerun_in(0) => clk_100,
gtwiz_reset_all_in(0) => rstall,
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
gtwiz_reset_rx_datapath_in => "0",
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out(0) => txresetdone,
gtwiz_reset_rx_done_out(0) => rxresetdone,
gtwiz_userdata_tx_in(15 downto 0) => gt03_datatx,
gtwiz_userdata_tx_in(31 downto 16) => gt02_datatx,
gtwiz_userdata_tx_in(47 downto 32) => gt04_datatx,
gtwiz_userdata_tx_in(63 downto 48) => gt01_datatx,
gtwiz_userdata_rx_out(15 downto 0) => gt03_datarx,
gtwiz_userdata_rx_out(31 downto 16) => gt02_datarx,
gtwiz_userdata_rx_out(47 downto 32) => gt04_datarx,
gtwiz_userdata_rx_out(63 downto 48) => gt01_datarx,
gtrefclk01_in(0) => ref_clk,
qpll1lock_out(0) => qplllock,
qpll1outclk_out => open,
qpll1outrefclk_out => open,
gthrxn_in(0) => sfp03_rxn,
gthrxn_in(1) => sfp02_rxn,
gthrxn_in(2) => sfp04_rxn,
gthrxn_in(3) => sfp01_rxn,
gthrxp_in(0) => sfp03_rxp,
gthrxp_in(1) => sfp02_rxp,
gthrxp_in(2) => sfp04_rxp,
gthrxp_in(3) => sfp01_rxp,
rxbufreset_in => (others => '0'),
rx8b10ben_in => (others => '1'),
rxcommadeten_in(0) => gt03_rxcommadeten,
rxcommadeten_in(1) => gt02_rxcommadeten,
rxcommadeten_in(2) => gt04_rxcommadeten,
rxcommadeten_in(3) => gt01_rxcommadeten,
rxmcommaalignen_in => (others => '1'),
rxpcommaalignen_in => (others => '1'),
tx8b10ben_in => (others => '1'),
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gthtxn_out(0) => sfp03_txn,
gthtxn_out(1) => sfp02_txn,
gthtxn_out(2) => sfp04_txn,
gthtxn_out(3) => sfp01_txn,
gthtxp_out(0) => sfp03_txp,
gthtxp_out(1) => sfp02_txp,
gthtxp_out(2) => sfp04_txp,
gthtxp_out(3) => sfp01_txp,
gtpowergood_out(0) => gt03_powergood,
gtpowergood_out(1) => gt02_powergood,
gtpowergood_out(2) => gt04_powergood,
gtpowergood_out(3) => gt01_powergood,
rxbufstatus_out => open,
rxbyteisaligned_out(0) => gt03_rxbyteisaligned,
rxbyteisaligned_out(1) => gt02_rxbyteisaligned,
rxbyteisaligned_out(2) => gt04_rxbyteisaligned,
rxbyteisaligned_out(3) => gt01_rxbyteisaligned,
rxbyterealign_out(0) => gt03_rxbyterealign,
rxbyterealign_out(1) => gt02_rxbyterealign,
rxbyterealign_out(2) => gt04_rxbyterealign,
rxbyterealign_out(3) => gt01_rxbyterealign,
rxcdrlock_out(0) => gt03_rxcdrlock,
rxcdrlock_out(1) => gt02_rxcdrlock,
rxcdrlock_out(2) => gt04_rxcdrlock,
rxcdrlock_out(3) => gt01_rxcdrlock,
rxclkcorcnt_out => open,
rxcommadet_out(0) => gt03_rxcommadet,
rxcommadet_out(1) => gt02_rxcommadet,
rxcommadet_out(2) => gt04_rxcommadet,
rxcommadet_out(3) => gt01_rxcommadet,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open
);
----------------------
-- DIRECT CONNEXION --
----------------------
gt01_txfault <= sfp01_tx_fault;
gt02_txfault <= sfp02_tx_fault;
gt03_txfault <= sfp03_tx_fault;
gt04_txfault <= sfp04_tx_fault;
gt01_rxlos <= sfp01_rx_los;
gt02_rxlos <= sfp02_rx_los;
gt03_rxlos <= sfp03_rx_los;
gt04_rxlos <= sfp04_rx_los;
gt01_modabs <= sfp01_mod_abs;
gt02_modabs <= sfp02_mod_abs;
gt03_modabs <= sfp03_mod_abs;
gt04_modabs <= sfp04_mod_abs;
sfp01_tx_disable <= gt01_txdisable;
sfp02_tx_disable <= gt02_txdisable;
sfp03_tx_disable <= gt03_txdisable;
sfp04_tx_disable <= gt04_txdisable;
end architecture rtl;
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-- This file was automatically generated with HECTARE
--
-- DO NOT EDIT
--
-- input_filename = combpm_protocol_electron_ctrl.rdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity combpm_protocol_electron_ctrl_axi is
generic(
G_ADDR_W: integer := 8
);
port (
sfp_txfault_i : in std_logic;
sfp_rxlos_i : in std_logic;
sfp_modabs_i : in std_logic;
sfp_txdisable_o : out std_logic;
gt_powergood_i : in std_logic;
gt_qplllock_i : in std_logic;
gt_txclkactive_i : in std_logic;
gt_rxclkactive_i : in std_logic;
gt_rxcdrlock_i : in std_logic;
gt_txresetdone_i : in std_logic;
gt_rxresetdone_i : in std_logic;
gt_rxbyteisaligned_i : in std_logic;
gt_rxbyterealign_i : in std_logic;
gt_rxcommadet_i : in std_logic;
gt_rxcommadeten_o : out std_logic;
gt_rstall_o : out std_logic;
protocol_framecnt_i : in std_logic_vector(15 downto 0);
protocol_frameerror_i : in std_logic;
clk : in std_logic;
reset : in std_logic;
S_AXI_AWADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(G_ADDR_W-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end entity;
architecture arch of combpm_protocol_electron_ctrl_axi is
-- address constants
constant C_ADDR_SFP : integer := 0;
constant C_ADDR_GT : integer := 1;
constant C_ADDR_PROTOCOL : integer := 2;
-- field ranges constants
constant C_FIELD_SFP_TXFAULT_MSB : integer := 0;
constant C_FIELD_SFP_TXFAULT_LSB : integer := 0;
constant C_FIELD_SFP_RXLOS_MSB : integer := 1;
constant C_FIELD_SFP_RXLOS_LSB : integer := 1;
constant C_FIELD_SFP_MODABS_MSB : integer := 2;
constant C_FIELD_SFP_MODABS_LSB : integer := 2;
constant C_FIELD_SFP_TXDISABLE_MSB : integer := 3;
constant C_FIELD_SFP_TXDISABLE_LSB : integer := 3;
constant C_FIELD_GT_POWERGOOD_MSB : integer := 0;
constant C_FIELD_GT_POWERGOOD_LSB : integer := 0;
constant C_FIELD_GT_QPLLLOCK_MSB : integer := 1;
constant C_FIELD_GT_QPLLLOCK_LSB : integer := 1;
constant C_FIELD_GT_TXCLKACTIVE_MSB : integer := 2;
constant C_FIELD_GT_TXCLKACTIVE_LSB : integer := 2;
constant C_FIELD_GT_RXCLKACTIVE_MSB : integer := 3;
constant C_FIELD_GT_RXCLKACTIVE_LSB : integer := 3;
constant C_FIELD_GT_RXCDRLOCK_MSB : integer := 4;
constant C_FIELD_GT_RXCDRLOCK_LSB : integer := 4;
constant C_FIELD_GT_TXRESETDONE_MSB : integer := 5;
constant C_FIELD_GT_TXRESETDONE_LSB : integer := 5;
constant C_FIELD_GT_RXRESETDONE_MSB : integer := 6;
constant C_FIELD_GT_RXRESETDONE_LSB : integer := 6;
constant C_FIELD_GT_RXBYTEISALIGNED_MSB : integer := 7;
constant C_FIELD_GT_RXBYTEISALIGNED_LSB : integer := 7;
constant C_FIELD_GT_RXBYTEREALIGN_MSB : integer := 8;
constant C_FIELD_GT_RXBYTEREALIGN_LSB : integer := 8;
constant C_FIELD_GT_RXCOMMADET_MSB : integer := 9;
constant C_FIELD_GT_RXCOMMADET_LSB : integer := 9;
constant C_FIELD_GT_RXCOMMADETEN_MSB : integer := 10;
constant C_FIELD_GT_RXCOMMADETEN_LSB : integer := 10;
constant C_FIELD_GT_RSTALL_MSB : integer := 11;
constant C_FIELD_GT_RSTALL_LSB : integer := 11;
constant C_FIELD_PROTOCOL_FRAMECNT_MSB : integer := 15;
constant C_FIELD_PROTOCOL_FRAMECNT_LSB : integer := 0;
constant C_FIELD_PROTOCOL_FRAMEERROR_MSB : integer := 16;
constant C_FIELD_PROTOCOL_FRAMEERROR_LSB : integer := 16;
-- registers
signal reg_sfp : std_logic_vector(32-1 downto 0);
signal reg_gt : std_logic_vector(32-1 downto 0);
signal reg_protocol : std_logic_vector(32-1 downto 0);
-- read
type t_state_read is (sReadIdle, sReadValid);
signal state_read : t_state_read;
signal rdata_reg : std_logic_vector(31 downto 0);
signal raddr_word : integer;
signal arready_wire : std_logic;
signal rvalid_wire : std_logic;
-- write
type t_state_write is (sWriteIdle, sWriteWaitData, sWriteWaitAddr, sWriteResp);
signal state_write : t_state_write;
signal state_write_prev : t_state_write;
signal waddr_reg : std_logic_vector(G_ADDR_W-1 downto 0);
signal wdata_reg : std_logic_vector(31 downto 0);
signal waddr_word : integer;
signal awready_wire : std_logic;
signal wready_wire : std_logic;
signal bvalid_wire : std_logic;
begin
reg_sfp(0) <= sfp_txfault_i when rising_edge(clk);
reg_sfp(1) <= sfp_rxlos_i when rising_edge(clk);
reg_sfp(2) <= sfp_modabs_i when rising_edge(clk);
sfp_txdisable_o <= reg_sfp(3);
reg_gt(0) <= gt_powergood_i when rising_edge(clk);
reg_gt(1) <= gt_qplllock_i when rising_edge(clk);
reg_gt(2) <= gt_txclkactive_i when rising_edge(clk);
reg_gt(3) <= gt_rxclkactive_i when rising_edge(clk);
reg_gt(4) <= gt_rxcdrlock_i when rising_edge(clk);
reg_gt(5) <= gt_txresetdone_i when rising_edge(clk);
reg_gt(6) <= gt_rxresetdone_i when rising_edge(clk);
reg_gt(7) <= gt_rxbyteisaligned_i when rising_edge(clk);
reg_gt(8) <= gt_rxbyterealign_i when rising_edge(clk);
reg_gt(9) <= gt_rxcommadet_i when rising_edge(clk);
gt_rxcommadeten_o <= reg_gt(10);
gt_rstall_o <= reg_gt(11);
reg_protocol(15 downto 0) <= protocol_framecnt_i when rising_edge(clk);
reg_protocol(16) <= protocol_frameerror_i when rising_edge(clk);
proc_state_read: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
state_read <= sReadIdle;
else
case state_read is
when sReadIdle =>
if S_AXI_ARVALID = '1' then
state_read <= sReadValid;
end if;
when sReadValid =>
if S_AXI_RREADY = '1' then
state_read <= sReadIdle;
end if;
end case;
end if;
end if;
end process;
raddr_word <= to_integer(unsigned(S_AXI_ARADDR(G_ADDR_W-1 downto 2)));
-- ### read logic
proc_rdata_reg: process (clk)
begin
if rising_edge(clk) then
rdata_reg <= (others => '0');
case raddr_word is
when C_ADDR_SFP =>
rdata_reg(0 downto 0) <= reg_sfp(0 downto 0);
rdata_reg(1 downto 1) <= reg_sfp(1 downto 1);
rdata_reg(2 downto 2) <= reg_sfp(2 downto 2);
rdata_reg(3 downto 3) <= reg_sfp(3 downto 3);
when C_ADDR_GT =>
rdata_reg(0 downto 0) <= reg_gt(0 downto 0);
rdata_reg(1 downto 1) <= reg_gt(1 downto 1);
rdata_reg(2 downto 2) <= reg_gt(2 downto 2);
rdata_reg(3 downto 3) <= reg_gt(3 downto 3);
rdata_reg(4 downto 4) <= reg_gt(4 downto 4);
rdata_reg(5 downto 5) <= reg_gt(5 downto 5);
rdata_reg(6 downto 6) <= reg_gt(6 downto 6);
rdata_reg(7 downto 7) <= reg_gt(7 downto 7);
rdata_reg(8 downto 8) <= reg_gt(8 downto 8);
rdata_reg(9 downto 9) <= reg_gt(9 downto 9);
rdata_reg(10 downto 10) <= reg_gt(10 downto 10);
rdata_reg(11 downto 11) <= reg_gt(11 downto 11);
when C_ADDR_PROTOCOL =>
rdata_reg(15 downto 0) <= reg_protocol(15 downto 0);
rdata_reg(16 downto 16) <= reg_protocol(16 downto 16);
when others =>
-- decode error
rdata_reg <= x"badc0fee";
end case;
end if;
end process;
proc_read_output: process (state_read)
begin
case state_read is
when sReadIdle =>
arready_wire <= '1';
rvalid_wire <= '0';
when sReadValid =>
arready_wire <= '0';
rvalid_wire <= '1';
when others =>
arready_wire <= '0';
rvalid_wire <= '0';
end case;
end process;
S_AXI_ARREADY <= arready_wire;
S_AXI_RVALID <= rvalid_wire;
S_AXI_RDATA <= rdata_reg;
S_AXI_RRESP <= "00";
proc_state_write_prev: process (clk) begin
if rising_edge(clk) then
state_write_prev <= state_write;
end if;
end process;
proc_state_write: process (clk) begin
if rising_edge (clk) then
if reset = '1' then
state_write <= sWriteIdle;
else
case state_write is
when sWriteIdle =>
if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
wdata_reg <= S_AXI_WDATA;
elsif S_AXI_AWVALID = '1' and S_AXI_WVALID = '0' then
state_write <= sWriteWaitData;
waddr_reg <= S_AXI_AWADDR;
elsif S_AXI_AWVALID = '0' and S_AXI_WVALID = '1' then
state_write <= sWriteWaitAddr;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitData =>
if S_AXI_WVALID = '1' then
state_write <= sWriteResp;
wdata_reg <= S_AXI_WDATA;
end if;
when sWriteWaitAddr =>
if S_AXI_AWVALID = '1' then
state_write <= sWriteResp;
waddr_reg <= S_AXI_AWADDR;
end if;
when sWriteResp =>
if S_AXI_BREADY = '1' then
state_write <= sWriteIdle;
end if;
end case;
end if;
end if;
end process;
waddr_word <= to_integer(unsigned(waddr_reg(G_ADDR_W-1 downto 2)));
-- ### write logic (use waddr_word and wdata_reg)
proc_write: process (clk) begin
if rising_edge(clk) then
if reset = '1' then
reg_sfp(3 downto 3) <= "0";
reg_gt(10 downto 10) <= "1";
reg_gt(11 downto 11) <= "1";
else
-- default (pulse)
-- default (swmod)
-- default (woclr)
if state_write = sWriteResp and state_write_prev /= sWriteResp then
case waddr_word is
when C_ADDR_SFP =>
reg_sfp(3 downto 3) <= wdata_reg(3 downto 3);
when C_ADDR_GT =>
reg_gt(10 downto 10) <= wdata_reg(10 downto 10);
reg_gt(11 downto 11) <= wdata_reg(11 downto 11);
when C_ADDR_PROTOCOL =>
null;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
proc_write_output: process (state_write) begin
case state_write is
when sWriteIdle =>
awready_wire <= '1';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitData =>
awready_wire <= '0';
wready_wire <= '1';
bvalid_wire <= '0';
when sWriteWaitAddr =>
awready_wire <= '1';
wready_wire <= '0';
bvalid_wire <= '0';
when sWriteResp =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '1';
when others =>
awready_wire <= '0';
wready_wire <= '0';
bvalid_wire <= '0';
end case;
end process;
S_AXI_AWREADY <= awready_wire;
S_AXI_WREADY <= wready_wire;
S_AXI_BRESP <= "00";
S_AXI_BVALID <= bvalid_wire;
end architecture;
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