Fix simulation test

* Change the testbench interface
* Add a very simple script to compile and bring up GUI

scripts/test.sh

+#!/bin/bash
+
+# Perform compilation of all vhdl sources
+# For test, only two are needed, but it helps to check syntax
+# This will create xsim.dir/work
+xvhdl --log test.log hdl/combpm_protocol_electron_ctrl.vhd
+xvhdl --log test.log hdl/combpm_protocol_electron.vhd
+xvhdl --log test.log hdl/top_combpm_electron.vhd
+xvhdl --log test.log test/tb_combpm_protocol_electron.vhd
+
+# Perform Elaboration and snapshot creation
+# This will create xsim.dir/work.tb_combpm_protocol_electron
+xelab tb_combpm_protocol_electron -debug typical
+
+# Launch simulation
+xsim work.tb_combpm_protocol_electron -view test/tb_combpm_protocol_electron_behav.wcfg -gui

test/tb_combpm_protocol_electron.vhd

@@ -13,63 +13,47 @@ end entity;
 
 architecture testbench of tb_combpm_protocol_electron is
 
-    file file_input : text open read_mode is "input.txt";
-
-    signal tb_clk : std_logic := '0';
-    signal tb_rstn : std_logic := '1';
-
-    signal tb_gt_datarx : std_logic_vector(15 downto 0);
-    signal tb_gt_datatx : std_logic_vector(15 downto 0);
-    signal tb_gt_powergood : std_logic;
-    signal tb_gt_qplllock : std_logic;
-    signal tb_gt_txclkactive : std_logic;
-    signal tb_gt_rxclkactive : std_logic;
-    signal tb_gt_txresetdone : std_logic;
-    signal tb_gt_rxresetdone : std_logic;
-    signal tb_gt_rxcdrlock : std_logic;
+    file file_input              : text open read_mode is "test/input.txt";
+
+    signal tb_clk                : std_logic                           := '0';
+    signal tb_rstn               : std_logic                           := '1';
+
+    signal tb_gt_datarx          : std_logic_vector(15 downto 0);
+    signal tb_gt_datatx          : std_logic_vector(15 downto 0);
+    signal tb_gt_powergood       : std_logic;
+    signal tb_gt_qplllock        : std_logic;
+    signal tb_gt_txclkactive     : std_logic;
+    signal tb_gt_rxclkactive     : std_logic;
+    signal tb_gt_txresetdone     : std_logic;
+    signal tb_gt_rxresetdone     : std_logic;
+    signal tb_gt_rxcdrlock       : std_logic;
     signal tb_gt_rxbyteisaligned : std_logic;
-    signal tb_gt_rxbyterealign : std_logic;
-    signal tb_gt_rxcommadet : std_logic;
-    signal tb_gt_txfault : std_logic;
-    signal tb_gt_rxlos : std_logic;
-    signal tb_gt_modabs : std_logic;
-    signal tb_gt_rstall : std_logic;
-    signal tb_gt_rxcommadeten : std_logic;
-    signal tb_gt_txdisable : std_logic;
-
-    signal tb_m_axi_tid : std_logic_vector(0 downto 0);
-    signal tb_m_axi_tdest : std_logic_vector(9 downto 0);
-    signal tb_m_axi_tdata : std_logic_vector(127 downto 0);
-    signal tb_m_axi_tstrb : std_logic_vector(15 downto 0);
-    signal tb_m_axi_tkeep : std_logic_vector(15 downto 0);
-    signal tb_m_axi_tlast : std_logic;
-    signal tb_m_axi_tuser : std_logic_vector(0 downto 0);
-    signal tb_m_axi_tvalid : std_logic;
-    signal tb_m_axi_tready : std_logic;
-
-    signal tb_s_axi_clk     : std_logic;
-    signal tb_s_axi_resetn  : std_logic;
-    signal tb_s_axi_awaddr  : std_logic_vector(7 downto 0);
-    signal tb_s_axi_awprot  : std_logic_vector(2 downto 0);
-    signal tb_s_axi_awvalid : std_logic;
-    signal tb_s_axi_awready : std_logic;
-    signal tb_s_axi_wdata   : std_logic_vector(32-1 downto 0);
-    signal tb_s_axi_wstrb   : std_logic_vector(32/8-1 downto 0);
-    signal tb_s_axi_wvalid  : std_logic;
-    signal tb_s_axi_wready  : std_logic;
-    signal tb_s_axi_bresp   : std_logic_vector(1 downto 0);
-    signal tb_s_axi_bvalid  : std_logic;
-    signal tb_s_axi_bready  : std_logic;
-    signal tb_s_axi_araddr  : std_logic_vector(7 downto 0);
-    signal tb_s_axi_arprot  : std_logic_vector(2 downto 0);
-    signal tb_s_axi_arvalid : std_logic;
-    signal tb_s_axi_arready : std_logic;
-    signal tb_s_axi_rdata   : std_logic_vector(32-1 downto 0);
-    signal tb_s_axi_rresp   : std_logic_vector(1 downto 0);
-    signal tb_s_axi_rvalid  : std_logic;
-    signal tb_s_axi_rready  : std_logic;
-
-    signal test_done : boolean := False;
+    signal tb_gt_rxbyterealign   : std_logic;
+    signal tb_gt_rxcommadet      : std_logic;
+    signal tb_gt_txfault         : std_logic;
+    signal tb_gt_rxlos           : std_logic;
+    signal tb_gt_modabs          : std_logic;
+    signal tb_gt_rstall          : std_logic;
+    signal tb_gt_rxcommadeten    : std_logic;
+    signal tb_gt_txdisable       : std_logic;
+
+    signal tb_m_axi_tid          : std_logic_vector(0 downto 0);
+    signal tb_m_axi_tdest        : std_logic_vector(9 downto 0);
+    signal tb_m_axi_tdata        : std_logic_vector(127 downto 0);
+    signal tb_m_axi_tstrb        : std_logic_vector(15 downto 0);
+    signal tb_m_axi_tkeep        : std_logic_vector(15 downto 0);
+    signal tb_m_axi_tlast        : std_logic;
+    signal tb_m_axi_tuser        : std_logic_vector(0 downto 0);
+    signal tb_m_axi_tvalid       : std_logic;
+    signal tb_m_axi_tready       : std_logic;
+
+    signal tb_tx_disable_i       : std_logic;
+    signal tb_rx_commadeten_i    : std_logic;
+    signal tb_srst_gt_i          : std_logic;
+    signal tb_frame_counter_o    : std_logic_vector(15 downto 0);
+    signal tb_frame_error_o      : std_logic;
+
+    signal test_done             : boolean                             := False;
 
 begin
 
@@ -112,6 +96,9 @@ begin
         end loop;
         tb_rstn <= '0';
         tb_gt_datarx <= (others => '1');
+        tb_srst_gt_i <= '0';
+        tb_tx_disable_i <= '1';
+        tb_rx_commadeten_i <= '1';
 
         -- Wait and deassert reset
         for I in 0 to 10 loop
@@ -140,18 +127,12 @@ begin
 
     end process;
 
-    --------------------
-    -- AXI CONNEXIONS --
-    --------------------
-    tb_s_axi_clk <= '0';
-    tb_s_axi_resetn <= '0';
-
     -----------------------
     -- DUT INSTANCIATION --
     -----------------------
     dut_inst: entity work.combpm_protocol_electron
     port map(
-        gt_clk => tb_clk,
+        clk => tb_clk,
         rst_n => tb_rstn,
         gt_datarx => tb_gt_datarx,
         gt_datatx => tb_gt_datatx,
@@ -180,28 +161,11 @@ begin
         m_axi_tuser => tb_m_axi_tuser,
         m_axi_tvalid => tb_m_axi_tvalid,
         m_axi_tready => tb_m_axi_tready,
-        S_AXI_CLK     => tb_s_axi_clk,
-        S_AXI_RESETN  => tb_s_axi_resetn,
-        S_AXI_AWADDR  => tb_s_axi_awaddr,
-        S_AXI_AWPROT  => tb_s_axi_awprot,
-        S_AXI_AWVALID => tb_s_axi_awvalid,
-        S_AXI_AWREADY => tb_s_axi_awready,
-        S_AXI_WDATA   => tb_s_axi_wdata,
-        S_AXI_WSTRB   => tb_s_axi_wstrb,
-        S_AXI_WVALID  => tb_s_axi_wvalid,
-        S_AXI_WREADY  => tb_s_axi_wready,
-        S_AXI_BRESP   => tb_s_axi_bresp,
-        S_AXI_BVALID  => tb_s_axi_bvalid,
-        S_AXI_BREADY  => tb_s_axi_bready,
-        S_AXI_ARADDR  => tb_s_axi_araddr,
-        S_AXI_ARPROT  => tb_s_axi_arprot,
-        S_AXI_ARVALID => tb_s_axi_arvalid,
-        S_AXI_ARREADY => tb_s_axi_arready,
-        S_AXI_RDATA   => tb_s_axi_rdata,
-        S_AXI_RRESP   => tb_s_axi_rresp,
-        S_AXI_RVALID  => tb_s_axi_rvalid,
-        S_AXI_RREADY  => tb_s_axi_rready
-
+        tx_disable_i       => tb_tx_disable_i,
+        rx_commadeten_i    => tb_rx_commadeten_i,
+        srst_gt_i          => tb_srst_gt_i,
+        frame_counter_o    => tb_frame_counter_o,
+        frame_error_o      => tb_frame_error_o
     );
 
 end architecture testbench;