* Put configuration in a variable to print it
* Put the quad_name in a variable, not fully used by now.
* Set the target FPGA in the TCL.

* Remove Makefile.
* Add tcl/main.tcl with mandatory functions.
* change tcl to create the GT wizard.

* Do not allow to start CRC computation right after a result
* CRC word counter up to 12 then roll over to 0

* Need at least SOP and EOP.
* If any other flag is missing, raise error

* Error detect can trigger an interrupt, a capture...
* More debug to understand situations

* Reset the register properly
* Add register in memory map bank

After check, the line rate is exactly 2.125 Gbps (20*106.25MHz)

Top level:
* Add MC time and PPS port
* GT Interface ready combinatorial inside top level

Protocol decoder
* New GT Interface ready input port
* New MC time and PPS input ports
* New output ports for new features
* Frame counters, frame rates
* Sequence checkers
* Change output AXIS packet : MC time, packet_time LSB only

AXI interface:
* Add registers for new features
* Fix Makefile rule for RDL->VHD

This modification are probably transparent. But it's better to be
accurate.

* Add FB and REF lost signals
* Add output of GT ref clock (through buffers)

* Add debug ports of transceiver data and status before the protocole
  decoder.
* Add a reset bit for PLL and datapath in AXI-MM interface.

* Connect true QPLL lock bit
* Attribute on QPLL_reset is now active high

* Also update the Makefile

* Remove unused signals

Also add Makefile rule to perform synthesis of IP bloc

* GTHE COMMON must be outside IP (QPLL needed for other interfaces)
* GTWizard created with TCL
* GTWizard instantiated directly in top level

* Remove package and XCI
* The parametrization will be made somehow differently

VHDL
* Add attributes on interface ports.
* Bring back QPLL andCDR lock signals on the GT wrapper

TCL
* Add simple address map

* Use a makefile to build the packaged IP

* Corrections for synthesis
* QPLL lock output signal TEMPORARY set to one   !!

* Use a package

* HTG2QSFP, on FMC1, Only 4 lanes

Calling this script will add VHDL and XCI source files to the current
project.

* Change the testbench interface
* Add a very simple script to compile and bring up GUI

* Wrap the protocol bloc and the aximm control in a structural top
  level.
* Get rid of the CDC, use only one clock. Domain crossing will be
  outside this bloc.

* Import sources from Cell Node initial project