* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.

Packet Filter
* Address width for memory is now a generic
* This width is a parameter for generation of xilinx ips
* fix for synthesis

COMBPM
* use package for COMBPM packet

package COMBPM
* new constant for zero packet

* Add a gitignore to ignore the generated file.
* For now, this package has no use.

* Rename the RDL file, and the addrmap name to match the module name.
* Add addAddressSpace that gives the RDL file path.

* Put configuration in a variable to print it
* Put the quad_name in a variable, not fully used by now.
* Set the target FPGA in the TCL.

* Remove Makefile.
* Add tcl/main.tcl with mandatory functions.
* change tcl to create the GT wizard.

After check, the line rate is exactly 2.125 Gbps (20*106.25MHz)

This modification are probably transparent. But it's better to be
accurate.

* Also update the Makefile

Also add Makefile rule to perform synthesis of IP bloc

* GTHE COMMON must be outside IP (QPLL needed for other interfaces)
* GTWizard created with TCL
* GTWizard instantiated directly in top level

* Remove package and XCI
* The parametrization will be made somehow differently

VHDL
* Add attributes on interface ports.
* Bring back QPLL andCDR lock signals on the GT wrapper

TCL
* Add simple address map

* Use a makefile to build the packaged IP