* Reset the register properly
* Add register in memory map bank

Top level:
* Add MC time and PPS port
* GT Interface ready combinatorial inside top level

Protocol decoder
* New GT Interface ready input port
* New MC time and PPS input ports
* New output ports for new features
* Frame counters, frame rates
* Sequence checkers
* Change output AXIS packet : MC time, packet_time LSB only

AXI interface:
* Add registers for new features
* Fix Makefile rule for RDL->VHD

* Add debug ports of transceiver data and status before the protocole
  decoder.
* Add a reset bit for PLL and datapath in AXI-MM interface.

* Connect true QPLL lock bit
* Attribute on QPLL_reset is now active high

* Remove unused signals

Also add Makefile rule to perform synthesis of IP bloc

* GTHE COMMON must be outside IP (QPLL needed for other interfaces)
* GTWizard created with TCL
* GTWizard instantiated directly in top level

VHDL
* Add attributes on interface ports.
* Bring back QPLL andCDR lock signals on the GT wrapper

TCL
* Add simple address map

* Use a makefile to build the packaged IP

* Corrections for synthesis
* QPLL lock output signal TEMPORARY set to one   !!

* Use a package

* HTG2QSFP, on FMC1, Only 4 lanes

* Wrap the protocol bloc and the aximm control in a structural top
  level.
* Get rid of the CDC, use only one clock. Domain crossing will be
  outside this bloc.

* Import sources from Cell Node initial project