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doc/main.adoc
View file @ 4458a90f
= Documentation
= COMBPM module documentation
// ================================================================================
== Description
This module provides several logic blocks to allow communication with BPM (Beam Position Monitor) electronics.
This has been built for a very precise situation (libera electron, damc-fmc2zup), but the architecture should allow modification and portability.
For now, it only provides RX communication from the DLS CC protocol (ITech libera electron).
The module has been designed for DAMC-FMC2ZUP targets, populated with a 4SFP+ FMC board (CAENels).
// ================================================================================
== Overview
=== Main operation: Top level
The basics of this module is in three blocs that are essentials for the application.
* *Transceiver bloc*. Used to deserialize the communication stream from the BPM. +
_For now it is a Xilinx GTWizard, configured for the Libera Electron DLS CC protocol specs (2Gbps, 16b words...)._
_This is tied to a specific transceiver input of the FPGA._
* *Protocol decoder bloc*. From the deserialized words, it decode the stream and get the essential data (BPM number, position, timestamp...).
It outputs it on a AXI-Stream interface. +
_For now, it parses Libera Electron DLS CC._
* *AXI-MM register interface*. Used to configure and monitor everything from an AXI-MM interface (CPU).
These three blocs are depicted in the image below.
It is to note that the clock domain used is the data clock, even for the register interface.
This clock is provided and can be used to clock the rest of the application and/or clock CDC on the AXI-MM and AXIS interface. +
_The actual __top_combpm_electron.vhd__ file provides these three blocs configured and connected for the Libera Electron and damc-fmc2zup application._
.Basic overview of combpm module
image::images/overview.svg[]
=== Additionnal blocs
The module provide additionnal blocs usefull for the application.
* Frame filter
// ================================================================================
== Details
=== Protocol decoder (electron)
* CRC check. If fails: drop the frame, pulse frame_error output and increase the error counter.
* Counts and gives the number of frame in the last DLS CC sequence receive.
* DLS CC Sequence number check. If discontinuous: pulse seq_discontinuity output and increase
=== BPM frame AXIS stream
The AXIS data provided by the protocol decoder is descibed in the file _pkg_bpmframe_stream.vhd_.
See this file to have up to date fields info.
* Frames are not cut into packets (TLAST always '1').
* No FIFO on output (TREADY is not used).
The application needs to either implement FIFO or accepts every frame (AXIS packet).
The frame rate depends on the signal input.
=== Transceivers
The TCL script combpm_gtwizard.tcl is used to create the GTWizard IP, wich is instanciated in the top level.
=== AXI-MM register interface
We use DESYRDL to generate a AXI4L slave decoder.
=== Frame filter
*To be completed...*
// ================================================================================
== TODO/Future of this module
* Add configuration feature to allow the choice of the transceiver (for now only X0Y4 GTH).
* The application should be able to instanciate several transceiver interface, with one decoder for each.
* At SOLEIL, the BPM electronics will change by 2025.
At that point, it will be necessary to change the *Transceivers* and *Protocol decoder* blocs to match the new equipments.
hdl/combpm_packet_filter.vhd 0 → 100644
View file @ 4458a90f
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_bpmframe_stream.all;
entity combpm_packet_filter is
generic(
G_B_ADDR_W : natural := 14
);
port(
axis_clk : in std_logic;
axi_clk : in std_logic;
axis_rst_n : in std_logic;
axi_rst_n : in std_logic;
-- AXIS SLAVE INTERFACE
s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0);
s_axis_tdata : in std_logic_vector(C_TDATA_W-1 downto 0);
s_axis_tlast : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
-- AXIS SLAVE INTERFACE
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tlast : out std_logic;
m_axis_tvalid : out std_logic;
-- AXI bus interface
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
end combpm_packet_filter;
architecture rtl of combpm_packet_filter is
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT combpm_packet_filter_axi_bram_ctrl
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT combpm_packet_filter_blk_mem
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(G_B_ADDR_W-1 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal in_packet : t_bpmframe;
signal out_packet : t_bpmframe;
signal bram_clk_a : STD_LOGIC;
signal bram_en_a : STD_LOGIC;
signal bram_we_a : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal bram_addr_a : STD_LOGIC_VECTOR(G_B_ADDR_W-3 DOWNTO 0);
signal bram_wrdata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal bram_rddata_a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal table_data : std_logic_vector(7 downto 0);
signal tvalid_r : std_logic_vector(1 downto 0);
signal zero_packet : std_logic_vector(C_TDATA_W-1 downto 0);
begin
zero_packet <= (others => '0');
-- always ready
s_axis_tready <= '1';
----------------------
-- STREAM REGISTERS --
----------------------
p_main: process(axis_clk, axis_rst_n)
begin
if axis_rst_n = '0' then
in_packet <= slv2bpmframe(zero_packet);
out_packet <= slv2bpmframe(zero_packet);
elsif rising_edge(axis_clk) then
-- Register input packet
if s_axis_tvalid = '1' then
in_packet <= slv2bpmframe(s_axis_tdata);
end if;
tvalid_r(tvalid_r'left downto 1) <= tvalid_r(tvalid_r'left-1 downto 0);
tvalid_r(0) <= s_axis_tvalid;
out_packet <= in_packet;
end if;
end process;
-----------------
-- AXIS OUTPUT --
-----------------
m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W));
m_axis_tdata <= bpmframe2slv(out_packet);
m_axis_tlast <= '1'; -- Packet is one tdata only
m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
---------------------
-- BRAM CONTROLLER --
---------------------
inst_bram_ctrl : combpm_packet_filter_axi_bram_ctrl
port map (
s_axi_aclk => axi_clk,
s_axi_aresetn => axi_rst_n,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
bram_rst_a => open,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a(1 downto 0) => open,
bram_addr_a(G_B_ADDR_W-1 downto 2) => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a
);
-------------------
-- BRAM INSTANCE --
-------------------
inst_bram : combpm_packet_filter_blk_mem
port map(
clka => bram_clk_a,
ena => bram_en_a,
wea => bram_we_a,
addra => bram_addr_a,
dina => bram_wrdata_a,
douta => bram_rddata_a,
clkb => axis_clk,
enb => '1',
web => "0",
addrb => in_packet.bpm_id(G_B_ADDR_W-1 downto 0),
dinb => (others => '0'),
doutb => table_data
);
end architecture rtl;
hdl/combpm_protocol_electron.vhd
View file @ 4458a90f
......@@ -3,39 +3,33 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg_bpmframe_stream.all;
entity combpm_protocol_electron is
port(
rst_n : in std_logic;
clk : in std_logic;
pps : in std_logic;
rst_n : in std_logic; -- Asynchronous active low reset.
clk : in std_logic; -- Clock synchronous to data input.
pps : in std_logic; -- One pulse per second. Used for frame rate estimation.
mc_time : in std_logic_vector(39 downto 0);
mc_time : in std_logic_vector(39 downto 0); -- Machine clock time for frame time stamping.
-- GT interface
gt_datarx : in std_logic_vector(15 downto 0);
gt_interfaceready : in std_logic;
gt_datarx : in std_logic_vector(15 downto 0); -- Deserialized data.
-- AXIS interface
m_axi_tid : out std_logic_vector(0 downto 0);
m_axi_tdest : out std_logic_vector(9 downto 0);
m_axi_tdata : out std_logic_vector(127 downto 0);
m_axi_tstrb : out std_logic_vector(15 downto 0);
m_axi_tkeep : out std_logic_vector(15 downto 0);
m_axi_tlast : out std_logic;
m_axi_tuser : out std_logic_vector(0 downto 0);
m_axi_tvalid : out std_logic;
m_axi_tready : in std_logic;
m_axis_m2s : out t_bpmframe_axis_m2s;
m_axis_s2m : in t_bpmframe_axis_s2m;
-- Status and control interface
soft_reset : in std_logic;
frame_seq_cnt : out std_logic_vector(15 downto 0);
frame_valid_cnt : out std_logic_vector(15 downto 0);
frame_invalid_cnt : out std_logic_vector(15 downto 0);
frame_valid_rate : out std_logic_vector(15 downto 0);
frame_invalid_rate : out std_logic_vector(15 downto 0);
cnt_seq_mismatch : out std_logic;
seq_discontinuity : out std_logic;
frame_error : out std_logic
soft_reset : in std_logic; -- Reset all counters.
frame_seq_cnt : out std_logic_vector(15 downto 0); -- Number of frame in last sequence.
frame_valid_cnt : out std_logic_vector(31 downto 0); -- Count of valid frames.
frame_invalid_cnt : out std_logic_vector(31 downto 0); -- Count of invalid frames.
frame_valid_rate : out std_logic_vector(31 downto 0); -- Valid frame rate.
frame_invalid_rate : out std_logic_vector(31 downto 0); -- Invalid frame rate.
cnt_seq_mismatch : out std_logic; -- Pulse for number of frame in sequence mismatch.
seq_discontinuity : out std_logic; -- Pulse for discontinuity in sequence number.
frame_error : out std_logic -- Pulse for frame error.
);
end entity combpm_protocol_electron;
......@@ -83,10 +77,13 @@ architecture rtl of combpm_protocol_electron is
signal last_cnt_seq_r : unsigned(15 downto 0);
signal cnt_frame_seq_r : unsigned(15 downto 0);
signal cnt_valid_r : unsigned(15 downto 0);
signal cnt_invalid_r : unsigned(15 downto 0);
signal rate_valid_r : unsigned(15 downto 0);
signal rate_invalid_r : unsigned(15 downto 0);
signal cnt_valid_r : unsigned(31 downto 0);
signal cnt_invalid_r : unsigned(31 downto 0);
signal rate_valid_r : unsigned(31 downto 0);
signal rate_invalid_r : unsigned(31 downto 0);
signal packet : t_bpmframe;
signal m_axi_tvalid : std_logic;
begin
......@@ -131,8 +128,8 @@ begin
'0';
-- Any and all flag
flag_all <= flag_sop and flag_eop and flag_dummy and flag_rsvd and flag_crc and gt_interfaceready;
flag_frame <= flag_sop and flag_eop and gt_interfaceready;
flag_all <= flag_sop and flag_eop and flag_dummy and flag_rsvd and flag_crc;
flag_frame <= flag_sop and flag_eop;
----------------------------
-- FRAME FIELD EXTRACTION --
......@@ -238,39 +235,34 @@ begin
--------------
-- AXIS OUT --
--------------
-- Static data
m_axi_tstrb <= (others => '1');
m_axi_tkeep <= (others => '1');
m_axi_tid <= "0";
m_axi_tuser <= "0";
m_axi_tlast <= '1'; -- One transfer is One packet.
m_axis_m2s.tdest <= (others => '0');
m_axis_m2s.tdata <= bpmframe2slv(packet);
m_axis_m2s.tlast <= '1'; -- One transfer is One packet.
m_axis_m2s.tvalid <= m_axi_tvalid;
p_axis:process(clk, rst_n)
begin
if rst_n = '0' then
m_axi_tdata <= (others => '0');
packet <= C_BPMFRAME_ZERO;
m_axi_tvalid <= '0';
m_axi_tdest <= (others => '0');
elsif rising_edge(clk) then
if flag_all = '1' then
-- Make AXIS packet
m_axi_tdata(31 downto 0) <= packet_ypos;
m_axi_tdata(63 downto 32) <= packet_xpos;
m_axi_tdata(103 downto 64) <= mc_time;
m_axi_tdata(111 downto 104) <= packet_timestamp(7 downto 0);
m_axi_tdata(127 downto 112) <= "000000" & packet_bpmid;
-- AXIS ancillary data
m_axi_tdest <= packet_bpmid;
packet.pos_x <= packet_xpos;
packet.pos_y <= packet_ypos;
packet.bpm_id <= "000000" & packet_bpmid;
packet.mc_timestamp <= mc_time;
packet.fa_seq <= packet_timestamp(7 downto 0);
-- AXIS TVALID
m_axi_tvalid <= '1';
else
-- Acknowledge transfer
if m_axi_tready = '1' then
if m_axis_s2m.tready = '1' then
m_axi_tvalid <= '0';
end if;
end if;
......
hdl/pkg_bpmframe_stream.vhd 0 → 100644
View file @ 4458a90f
-- Package BPMFRAME STREAM
-- this package describe the format of the AXI-Stream interface used by blocs of the module COMBPM.
--
-- The usefull things are :
-- * Two record types for port interfaces: t_bpmframe_axis_m2s and t_bpmframe_axis_s2m.
-- * One record type for frame fields: t_bpmframe.
-- * Two functions to transform TDATA (std_logic_vector) to/from t_bpmframe: slv2bpmframe and bpmframe2slv.
library ieee;
use ieee.std_logic_1164.all;
package pkg_bpmframe_stream is
----------------------
-- MACRO PARAMETERS --
----------------------
constant C_TDEST_W : natural := 7;
constant C_TDATA_W : natural := 128;
---------------------------------
-- AXIS MASTER/SLAVE INTERFACE --
---------------------------------
type t_bpmframe_axis_m2s is record
tdest : std_logic_vector(C_TDEST_W-1 downto 0);
tdata : std_logic_vector(C_TDATA_W-1 downto 0);
tlast : std_logic;
tvalid : std_logic;
end record t_bpmframe_axis_m2s;
type t_bpmframe_axis_s2m is record
tready : std_logic;
end record t_bpmframe_axis_s2m;
------------------------
-- AXIS STREAM PACKET --
------------------------
type t_bpmframe is record
pos_x : std_logic_vector(31 downto 0);
pos_y : std_logic_vector(31 downto 0);
bpm_id : std_logic_vector(15 downto 0);
mc_timestamp : std_logic_vector(39 downto 0);
fa_seq : std_logic_vector(7 downto 0);
end record t_bpmframe;
constant C_BPMFRAME_ZERO : t_bpmframe := (
pos_x => (others => '0'),
pos_y => (others => '0'),
bpm_id => (others => '0'),
mc_timestamp => (others => '0'),
fa_seq => (others => '0')
);
function slv2bpmframe(
signal tdata : std_logic_vector(C_TDATA_W-1 downto 0)
)
return t_bpmframe;
function bpmframe2slv(
signal packet : t_bpmframe
)
return std_logic_vector;
end package;
package body pkg_bpmframe_stream is
function slv2bpmframe(
signal tdata : std_logic_vector(C_TDATA_W-1 downto 0)
)
return t_bpmframe is
variable packet : t_bpmframe;
begin
packet.pos_x := tdata(31 downto 0);
packet.pos_y := tdata(63 downto 32);
packet.bpm_id := tdata(79 downto 64);
packet.mc_timestamp := tdata(119 downto 80);
packet.fa_seq := tdata(127 downto 120);
return packet;
end function;
function bpmframe2slv(
signal packet : t_bpmframe
)
return std_logic_vector is
begin
return packet.fa_seq & packet.mc_timestamp & packet.bpm_id & packet.pos_y & packet.pos_x;
end function;
end package body;
hdl/top_combpm_electron.vhd
View file @ 4458a90f
......@@ -11,8 +11,10 @@ use xpm.vcomponents.all;
library desyrdl;
use desyrdl.common.all;
use desyrdl.pkg_COMBPM.all;
use desyrdl.pkg_combpm.all;
use work.pkg_bpmframe_stream.all;
use work.pkg_combpm_version.all;
entity top_combpm_electron is
port(
......@@ -45,15 +47,8 @@ entity top_combpm_electron is
sfp_tx_fault : in std_logic;
-- AXIS interface
m_axis_tid : out std_logic_vector(0 downto 0);
m_axis_tdest : out std_logic_vector(9 downto 0);
m_axis_tdata : out std_logic_vector(127 downto 0);
m_axis_tstrb : out std_logic_vector(15 downto 0);
m_axis_tkeep : out std_logic_vector(15 downto 0);
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic_vector(0 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_m2s : out t_bpmframe_axis_m2s;
m_axis_s2m : in t_bpmframe_axis_s2m; -- warning: TREADY is ignored !
-- AXI bus interface
pi_s_top : in t_COMBPM_m2s;
......@@ -63,30 +58,6 @@ end top_combpm_electron;
architecture struct of top_combpm_electron is
--------------------------
-- INTERFACE ATTRIBUTES --
--------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO of qpll_reset : SIGNAL is "xilinx.com:signal:reset:1.0 qpll_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER of qpll_reset : SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
ATTRIBUTE X_INTERFACE_PARAMETER of clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
ATTRIBUTE X_INTERFACE_INFO of sfp_txn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_txp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rx_los: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp_mod_abs: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
COMPONENT combpm_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -148,16 +119,16 @@ architecture struct of top_combpm_electron is
------------------------
-- SIGNAL DECLARATION --
------------------------
signal sync_resetn : std_logic;
signal sync_reset : std_logic;
signal usrclk : std_logic;
signal rst : std_logic;
signal sync_resetn : std_logic; -- This is async reset with sync deassertion
signal sync_reset : std_logic; -- This is async reset with sync deassertion
signal usrclk : std_logic;
signal rst : std_logic;
signal frame_seq_cnt : std_logic_vector(15 downto 0);
signal frame_valid_cnt : std_logic_vector(15 downto 0);
signal frame_invalid_cnt : std_logic_vector(15 downto 0);
signal frame_valid_rate : std_logic_vector(15 downto 0);
signal frame_invalid_rate : std_logic_vector(15 downto 0);
signal frame_valid_cnt : std_logic_vector(31 downto 0);
signal frame_invalid_cnt : std_logic_vector(31 downto 0);
signal frame_valid_rate : std_logic_vector(31 downto 0);
signal frame_invalid_rate : std_logic_vector(31 downto 0);
signal cnt_seq_mismatch : std_logic;
signal seq_discontinuity : std_logic;
signal frame_error : std_logic;
......@@ -170,14 +141,13 @@ architecture struct of top_combpm_electron is
signal gt_rxbyterealign : std_logic;
signal gt_rxcommadet : std_logic;
signal interface_ready : std_logic;
signal addrmap_w : t_addrmap_COMBPM_in;
signal addrmap_r : t_addrmap_COMBPM_out;
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
begin
-- This CDC is used to deassert async reset in sync with the transceiver clock.
xpm_cdc_async_rst_inst : xpm_cdc_async_rst
generic map (
DEST_SYNC_FF => 4,
......@@ -212,9 +182,6 @@ begin
-- SFP direct connexion
sfp_tx_disable <= '1';
-- Interface Ready signal combinatorial
interface_ready <= gt_powergood and gt_rxresetdone and gt_rxbyteisaligned and qpll_lock;
----------------------
-- AXI-MM INTERFACE --
----------------------
......@@ -231,8 +198,7 @@ begin
);
--addrmap_w.ID.data.data <= C_ID;
--addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los;
addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs;
addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood;
......@@ -254,17 +220,9 @@ begin
clk => usrclk,
pps => pps,
gt_datarx => gt_datarx,
gt_interfaceready => interface_ready,
m_axi_tid => m_axis_tid,
m_axi_tdest => m_axis_tdest,
m_axi_tdata => m_axis_tdata,
m_axi_tstrb => m_axis_tstrb,
m_axi_tkeep => m_axis_tkeep,
m_axi_tlast => m_axis_tlast,
m_axi_tuser => m_axis_tuser,
m_axi_tvalid => m_axis_tvalid,
m_axi_tready => m_axis_tready,
m_axis_m2s => m_axis_m2s,
m_axis_s2m => m_axis_s2m,
mc_time => mc_time,
soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
......
others/combpm_gtwizard_gthe4_common_wrapper.v deleted 100644 → 0
View file @ dd8c8cc3
This diff is collapsed.
others/gthe_common.vhd deleted 100644 → 0
View file @ dd8c8cc3
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity gthe_common is
port(
-- Differential clock intput
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
-- Detection features
freerun_clk : in std_logic;
-- Buffered ref
buff_gtrefclk : out std_logic;
-- QPLL0 interface
qpll0reset : in std_logic;
qpll0lock : out std_logic;
qpll0outclk : out std_logic;
qpll0refclk : out std_logic;
qpll0fblost : out std_logic;
qpll0reflost : out std_logic;
-- QPLL0 interface
qpll1reset : in std_logic;
qpll1lock : out std_logic;
qpll1outclk : out std_logic;
qpll1refclk : out std_logic;
qpll1fblost : out std_logic;
qpll1reflost : out std_logic
);
end entity gthe_common;
architecture struct of gthe_common is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
signal gtrefclk : std_logic;
signal gtrefclk_out2 : std_logic;
component combpm_gtwizard_gthe4_common_wrapper
port(
GTHE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
GTHE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_PCIERATEQPLL0 : in std_logic_vector(2 downto 0);
GTHE4_COMMON_PCIERATEQPLL1 : in std_logic_vector(2 downto 0);
GTHE4_COMMON_PMARSVD0 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_PMARSVD1 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0CLKRSVD0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0CLKRSVD1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0FBDIV : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0LOCKDETCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0LOCKEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0PD : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0REFCLKSEL : in std_logic_vector(2 downto 0);
GTHE4_COMMON_QPLL0RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1CLKRSVD0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1CLKRSVD1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1FBDIV : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL1LOCKDETCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1LOCKEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1PD : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1REFCLKSEL : in std_logic_vector(2 downto 0);
GTHE4_COMMON_QPLL1RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLLRSVD1 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLLRSVD2 : in std_logic_vector(4 downto 0);
GTHE4_COMMON_QPLLRSVD3 : in std_logic_vector(4 downto 0);
GTHE4_COMMON_QPLLRSVD4 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_RCALENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0DATA : in std_logic_vector(24 downto 0);
GTHE4_COMMON_SDM0RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0TOGGLE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0WIDTH : in std_logic_vector(1 downto 0);
GTHE4_COMMON_SDM1DATA : in std_logic_vector(24 downto 0);
GTHE4_COMMON_SDM1RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM1TOGGLE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM1WIDTH : in std_logic_vector(1 downto 0);
GTHE4_COMMON_TCONGPI : in std_logic_vector(9 downto 0);
GTHE4_COMMON_TCONPOWERUP : in std_logic_vector(0 downto 0);
GTHE4_COMMON_TCONRESET : in std_logic_vector(1 downto 0);
GTHE4_COMMON_TCONRSVDIN1 : in std_logic_vector(1 downto 0);
GTHE4_COMMON_DRPDO : out std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPRDY : out std_logic_vector(0 downto 0);
GTHE4_COMMON_PMARSVDOUT0 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_PMARSVDOUT1 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0FBCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0LOCK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0OUTCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0OUTREFCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0REFCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1FBCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1LOCK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1OUTCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1OUTREFCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1REFCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLLDMONITOR0 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLLDMONITOR1 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_REFCLKOUTMONITOR0 : out std_logic_vector(0 downto 0);
GTHE4_COMMON_REFCLKOUTMONITOR1 : out std_logic_vector(0 downto 0);
GTHE4_COMMON_RXRECCLK0SEL : out std_logic_vector(1 downto 0);
GTHE4_COMMON_RXRECCLK1SEL : out std_logic_vector(1 downto 0);
GTHE4_COMMON_SDM0FINALOUT : out std_logic_vector(3 downto 0);
GTHE4_COMMON_SDM0TESTDATA : out std_logic_vector(14 downto 0);
GTHE4_COMMON_SDM1FINALOUT : out std_logic_vector(3 downto 0);
GTHE4_COMMON_SDM1TESTDATA : out std_logic_vector(14 downto 0);
GTHE4_COMMON_TCONGPO : out std_logic_vector(9 downto 0);
GTHE4_COMMON_TCONRSVDOUT0 : out std_logic_vector(0 downto 0)
);
end component;
begin
-- INPUT BUFFER
IBUFDS_GTE4_inst : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => gtrefclk,
ODIV2 => gtrefclk_out2,
CEB => '0',
I => gtrefclk_p,
IB => gtrefclk_n
);
BUFG_GT_inst : BUFG_GT
port map (
O => buff_gtrefclk,
CE => '1',
CEMASK => '1',
CLR => '0',
CLRMASK => '1',
DIV => "000",
I => gtrefclk_out2
);
-- TRANSCEIVER COMMON BLOCK
gthe4_common_wrapper_inst: combpm_gtwizard_gthe4_common_wrapper
port map(
GTHE4_COMMON_BGBYPASSB => "1",
GTHE4_COMMON_BGMONITORENB => "1",
GTHE4_COMMON_BGPDB => "1",
GTHE4_COMMON_BGRCALOVRD => "11111",
GTHE4_COMMON_BGRCALOVRDENB => "1",
GTHE4_COMMON_DRPADDR => "0000000000000000",
GTHE4_COMMON_DRPCLK => "0",
GTHE4_COMMON_DRPDI => "0000000000000000",
GTHE4_COMMON_DRPEN => "0",
GTHE4_COMMON_DRPWE => "0",
GTHE4_COMMON_GTGREFCLK0 => "0",
GTHE4_COMMON_GTGREFCLK1 => "0",
GTHE4_COMMON_GTNORTHREFCLK00 => "0",
GTHE4_COMMON_GTNORTHREFCLK01 => "0",
GTHE4_COMMON_GTNORTHREFCLK10 => "0",
GTHE4_COMMON_GTNORTHREFCLK11 => "0",
GTHE4_COMMON_GTREFCLK00(0) => gtrefclk,
GTHE4_COMMON_GTREFCLK01(0) => gtrefclk,
GTHE4_COMMON_GTREFCLK10 => "0",
GTHE4_COMMON_GTREFCLK11 => "0",
GTHE4_COMMON_GTSOUTHREFCLK00 => "0",
GTHE4_COMMON_GTSOUTHREFCLK01 => "0",
GTHE4_COMMON_GTSOUTHREFCLK10 => "0",
GTHE4_COMMON_GTSOUTHREFCLK11 => "0",
GTHE4_COMMON_PCIERATEQPLL0 => "000",
GTHE4_COMMON_PCIERATEQPLL1 => "000",
GTHE4_COMMON_PMARSVD0 => "00000000",
GTHE4_COMMON_PMARSVD1 => "00000000",
GTHE4_COMMON_QPLL0CLKRSVD0 => "0",
GTHE4_COMMON_QPLL0CLKRSVD1 => "0",
GTHE4_COMMON_QPLL0FBDIV => "00000000",
GTHE4_COMMON_QPLL0LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL0LOCKEN => "1",
GTHE4_COMMON_QPLL0PD => "0",
GTHE4_COMMON_QPLL0REFCLKSEL => "001",
GTHE4_COMMON_QPLL0RESET(0) => qpll0reset,
GTHE4_COMMON_QPLL1CLKRSVD0 => "0",
GTHE4_COMMON_QPLL1CLKRSVD1 => "0",
GTHE4_COMMON_QPLL1FBDIV => "00000000",
GTHE4_COMMON_QPLL1LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL1LOCKEN => "1",
GTHE4_COMMON_QPLL1PD => "0",
GTHE4_COMMON_QPLL1REFCLKSEL => "001",
GTHE4_COMMON_QPLL1RESET(0) => qpll1reset,
GTHE4_COMMON_QPLLRSVD1 => "00000000",
GTHE4_COMMON_QPLLRSVD2 => "00000",
GTHE4_COMMON_QPLLRSVD3 => "00000",
GTHE4_COMMON_QPLLRSVD4 => "00000000",
GTHE4_COMMON_RCALENB => "1",
GTHE4_COMMON_SDM0DATA => "0000000000000000000000000",
GTHE4_COMMON_SDM0RESET => "0",
GTHE4_COMMON_SDM0TOGGLE => "0",
GTHE4_COMMON_SDM0WIDTH => "00",
GTHE4_COMMON_SDM1DATA => "0010001011010000111001010",
GTHE4_COMMON_SDM1RESET => "0",
GTHE4_COMMON_SDM1TOGGLE => "0",
GTHE4_COMMON_SDM1WIDTH => "00",
GTHE4_COMMON_TCONGPI => "0000000000",
GTHE4_COMMON_TCONPOWERUP => "0",
GTHE4_COMMON_TCONRESET => "00",
GTHE4_COMMON_TCONRSVDIN1 => "00",
GTHE4_COMMON_DRPDO => open,
GTHE4_COMMON_DRPRDY => open,
GTHE4_COMMON_PMARSVDOUT0 => open,
GTHE4_COMMON_PMARSVDOUT1 => open,
GTHE4_COMMON_QPLL0FBCLKLOST(0) => qpll0fblost,
GTHE4_COMMON_QPLL0LOCK(0) => qpll0lock,
GTHE4_COMMON_QPLL0OUTCLK(0) => qpll0outclk,
GTHE4_COMMON_QPLL0OUTREFCLK(0) => qpll0refclk,
GTHE4_COMMON_QPLL0REFCLKLOST(0) => qpll0reflost,
GTHE4_COMMON_QPLL1FBCLKLOST(0) => qpll1reflost,
GTHE4_COMMON_QPLL1LOCK(0) => qpll1lock,
GTHE4_COMMON_QPLL1OUTCLK(0) => qpll1outclk,
GTHE4_COMMON_QPLL1OUTREFCLK(0) => qpll1refclk,
GTHE4_COMMON_QPLL1REFCLKLOST(0) => qpll1fblost,
GTHE4_COMMON_QPLLDMONITOR0 => open,
GTHE4_COMMON_QPLLDMONITOR1 => open,
GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
GTHE4_COMMON_REFCLKOUTMONITOR1 => open,
GTHE4_COMMON_RXRECCLK0SEL => open,
GTHE4_COMMON_RXRECCLK1SEL => open,
GTHE4_COMMON_SDM0FINALOUT => open,
GTHE4_COMMON_SDM0TESTDATA => open,
GTHE4_COMMON_SDM1FINALOUT => open,
GTHE4_COMMON_SDM1TESTDATA => open,
GTHE4_COMMON_TCONGPO => open,
GTHE4_COMMON_TCONRSVDOUT0 => open
);
end architecture struct;
others/gtwizard_ultrascale_v1_7_gthe4_common.v deleted 100644 → 0
View file @ dd8c8cc3
This diff is collapsed.
rdl/COMBPM.rdl → rdl/combpm.rdl
View file @ 4458a90f
`include "COMBPM.vh" // Auto generated from FWK
`include "combpm.vh" // Auto generated from FWK
addrmap COMBPM {
addrmap combpm {
desyrdl_generate_hdl = true;
desyrdl_interface = "AXI4L";
name="BPM protocol decoder controller";
reg {
field {
hw=w;sw=r;
} data[32];
} VERSION;
reg {
name="SFP status and control";
......@@ -127,13 +133,15 @@ addrmap COMBPM {
field {
desc="Valid frame counter";
hw=w;sw=r;
} VALIDFRAMECNT[16];
} CNT[32];
} VALIDFRAMECNT;
reg {
field {
desc="Invalid frame counter";
hw=w;sw=r;
} INVALIDFRAMECNT[16];
} FRAMECNT;
} CNT[32];
} INVALIDFRAMECNT;
reg {
name="Protocol frame rate";
......@@ -141,13 +149,15 @@ addrmap COMBPM {
field {
desc="Valid frame rate";
hw=w;sw=r;
} VALIDFRAMERATE[16];
} RATE[32];
} VALIDFRAMERATE;
reg {
field {
desc="Invalid frame rate";
hw=w;sw=r;
} INVALIDFRAMERATE[16];
} FRAMERATE;
} RATE[32];
} INVALIDFRAMERATE;
reg {
name="Protocol frame sequence";
......
scripts/add_files.tcl deleted 100644 → 0
View file @ dd8c8cc3
# This will add sources files and import IP for the com_bpm bloc
set module_root [file normalize [file dirname [file normalize [info script]]]/../]
add_files "$module_root/hdl/combpm_protocol_electron_ctrl.vhd"
add_files "$module_root/hdl/combpm_protocol_electron.vhd"
add_files "$module_root/hdl/combpm_gtwrapper.vhd"
add_files "$module_root/hdl/top_combpm_electron.vhd"
add_files "$module_root/hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd"
import_ip "$module_root/ip_cores/CAENELSSFP_1L.xci"
scripts/test.sh deleted 100755 → 0
View file @ dd8c8cc3
#!/bin/bash
# Perform compilation of all vhdl sources
# For test, only two are needed, but it helps to check syntax
# This will create xsim.dir/work
xvhdl --log test.log hdl/combpm_protocol_electron_ctrl.vhd
xvhdl --log test.log hdl/combpm_protocol_electron.vhd
xvhdl --log test.log hdl/top_combpm_electron.vhd
xvhdl --log test.log test/tb_combpm_protocol_electron.vhd
# Perform Elaboration and snapshot creation
# This will create xsim.dir/work.tb_combpm_protocol_electron
xelab tb_combpm_protocol_electron -debug typical
# Launch simulation
xsim work.tb_combpm_protocol_electron -view test/tb_combpm_protocol_electron_behav.wcfg -gui
tcl/bloc_synthesis.tcl deleted 100644 → 0
View file @ dd8c8cc3
# Source metadata
source ./tcl/metadata.tcl
# Create project
create_project synth_project -part ${part} -in_memory
set_property source_mgmt_mode All [current_project]
set_property IP_REPO_PATHS . [current_fileset]
update_ip_catalog
# Create instance of the IP
create_ip -vendor ${vlnv_vendor} -library "user" -name "combpm" -module_name combpm_0
# Generate output products
#generate_target all [get_ips combpm_0]
# Try synthesis
synth_ip [get_ips combpm_0]
close_project
tcl/combpm.tcl deleted 100644 → 0
View file @ dd8c8cc3
# Source metadata
source ./tcl/metadata.tcl
# Create project
set ip_project [create_project -name ${design} -part ${part} -in_memory ]
set_property top ${top} [current_fileset]
# Compilation order in auto
set_property source_mgmt_mode All ${ip_project}
# Read sources
source tcl/sources.tcl
# Generate Xilinx IP
source tcl/generate_gtwizard.tcl
# Compile order to auto
update_compile_order -fileset sources_1
# Package project
ipx::package_project
set ip_core [ipx::current_core]
set_property -dict ${ip_properties} ${ip_core}
set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
# Associate AX/AXIS interfaces and reset with clock
# Done in VHDL file
# Remove default address map
ipx::remove_memory_map [lindex [split [ipx::get_memory_maps]] 2] [ipx::current_core]
# Create Address map
set s_axi_mm [ipx::add_memory_map s_axi_ctrl [ipx::current_core]]
set_property slave_memory_map_ref s_axi_ctrl [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
set_property ENABLEMENT_PRESENCE required ${s_axi_mm}
set s_axi_blk [ipx::add_address_block registers ${s_axi_mm}]
set_property -dict { \
ACCESS "read-write" \
DESCRIPTION "Control and status registers" \
ENABLEMENT_PRESENCE required \
NAME "registers" \
RANGE 256 \
USAGE "register" \
WIDTH 8 \
} ${s_axi_blk}
# Save IP and close project
ipx::check_integrity ${ip_core}
ipx::save_core ${ip_core}
close_project
tcl/generate_combpm_packet_filter_ip.tcl 0 → 100644
View file @ 4458a90f
# Address width, on logic side (8 bits data access)
set b_addr_w 14
# Address width on AXI MM side (32 bits access)
set a_addr_w [expr $b_addr_w-2]
set a_depth [expr 1<<$a_addr_w]
set b_depth [expr 1<<$b_addr_w]
set xcipath [create_ip -name axi_bram_ctrl -vendor xilinx.com -library ip -version 4.1 -module_name combpm_packet_filter_axi_bram_ctrl]
set_property -dict [list \
CONFIG.PROTOCOL {AXI4} \
CONFIG.SUPPORTS_NARROW_BURST {0} \
CONFIG.SINGLE_PORT_BRAM {1} \
CONFIG.USE_ECC {0} \
CONFIG.BMG_INSTANCE {EXTERNAL} \
CONFIG.MEM_DEPTH $a_depth \
CONFIG.CLKIF.FREQ_HZ 250000000 \
CONFIG.DATA_WIDTH 32 \
] [get_ips combpm_packet_filter_axi_bram_ctrl]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
set xcipath [create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name combpm_packet_filter_blk_mem]
set_property -dict [list \
CONFIG.Memory_Type {True_Dual_Port_RAM} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Byte_Size {8} \
CONFIG.Write_Width_A {32} \
CONFIG.Write_Depth_A $a_depth \
CONFIG.Read_Width_A {32} \
CONFIG.Operating_Mode_A {WRITE_FIRST} \
CONFIG.Write_Width_B {8} \
CONFIG.Read_Width_B {8} \
CONFIG.Operating_Mode_B {WRITE_FIRST} \
CONFIG.Enable_B {Use_ENB_Pin} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortA_Output_of_Memory_Core {false} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Port_B_Clock {250} \
CONFIG.Port_B_Write_Rate {0} \
CONFIG.Port_B_Enable_Rate {100} \
] [get_ips combpm_packet_filter_blk_mem]
set_property GENERATE_SYNTH_CHECKPOINT 0 [get_files $xcipath]
tcl/main.tcl
View file @ 4458a90f
......@@ -15,34 +15,41 @@ proc init {} {
proc setSources {} {
variable Vhdl
# Generate VHDL package with modle version
genModVerFile VHDL ../hdl/pkg_version.vhd
# Generate VHDL package with modversion
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../others/gthe_common.vhd
lappend Vhdl ../others/combpm_gtwizard_gthe4_common_wrapper.v
lappend Vhdl ../others/gtwizard_ultrascale_v1_7_gthe4_common.v
lappend Vhdl ../hdl/pkg_bpmframe_stream.vhd
lappend Vhdl ../hdl/combpm_packet_filter.vhd
}
# ==============================================================================
proc setAddressSpace {} {
variable AddressSpace
addAddressSpace AddressSpace "COMBPM" RDL {} ../rdl/COMBPM.rdl
addAddressSpace AddressSpace "combpm" RDL {} ../rdl/combpm.rdl
}
# ==============================================================================
proc doOnCreate {} {
variable Vhdl
addSources Vhdl
# TODO sould probably get that part number from the project configuration
set fpga_part "xczu11eg-ffvc1760-2L-e"
set_property part ${fpga_part} [current_project]
set_property target_language VHDL [current_project]
# This module is only for vivado tool. End here for another tooltype.
if {$::fwfwk::ToolType ne "vivado"} {
puts "\n[ERROR] This module is only configured to work with Vivado"
exit -1
}
# Create GT wizard IP
source ../tcl/combpm_gtwizard.tcl
set_property part ${::fwfwk::FpgaPart} [current_project]
set_property target_language VHDL [current_project]
source combpm_gtwizard.tcl
source generate_combpm_packet_filter_ip.tcl
variable Vhdl
addSources Vhdl
}
# ==============================================================================
......
tcl/metadata.tcl deleted 100644 → 0
View file @ dd8c8cc3
set design "combpm"
set top top_combpm_electron
set part "xczu11eg-ffvc1760-2L-e"
set vlnv_vendor "synchrotron-soleil.fr"
set ip_properties [ list \
vendor ${vlnv_vendor} \
library "user" \
name ${design} \
version "1.0" \
taxonomy "/Communication_&_Networking/Serial_Interfaces" \
display_name "BPM Communication Decoder" \
description "Decode CC protocol (Electron) from a transceiver interface and generate AXIS frames" \
vendor_display_name "Synchrotron SOLEIL" \
company_url "http://www.synchrotron-soleil.fr" \
]
set family_lifecycle [list \
zynquplus{${part}} Beta \
]

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