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gtwizard_ultrascale_v1_7_gthe4_common.v
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BRONES Romain authored
Also add Makefile rule to perform synthesis of IP bloc
BRONES Romain authoredAlso add Makefile rule to perform synthesis of IP bloc
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gtwizard_ultrascale_v1_7_gthe4_common.v 45.91 KiB
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
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//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_9_gthe4_common #(
// -------------------------------------------------------------------------------------------------------------------
// Parameters relating to GTHE4_COMMON primitive
// -------------------------------------------------------------------------------------------------------------------
// primitive wrapper parameters which override corresponding GTHE4_COMMON primitive parameters
parameter [0:0] GTHE4_COMMON_AEN_QPLL0_FBDIV = 1'b1,
parameter [0:0] GTHE4_COMMON_AEN_QPLL1_FBDIV = 1'b1,
parameter [0:0] GTHE4_COMMON_AEN_SDM0TOGGLE = 1'b0,
parameter [0:0] GTHE4_COMMON_AEN_SDM1TOGGLE = 1'b0,
parameter [0:0] GTHE4_COMMON_A_SDM0TOGGLE = 1'b0,
parameter [8:0] GTHE4_COMMON_A_SDM1DATA_HIGH = 9'b000000000,
parameter [15:0] GTHE4_COMMON_A_SDM1DATA_LOW = 16'b0000000000000000,
parameter [0:0] GTHE4_COMMON_A_SDM1TOGGLE = 1'b0,