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gthe_common.vhd

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    gthe_common.vhd 12.16 KiB
    library ieee;
    use ieee.std_logic_1164.all;
    
    Library UNISIM;
    use UNISIM.vcomponents.all;
    
    entity gthe_common is
        port(
            -- Differential clock intput
            gtrefclk_p      : in std_logic;
            gtrefclk_n      : in std_logic;
    
            -- Detection features
            freerun_clk     : in std_logic;
    
            -- Buffered ref
            buff_gtrefclk   : out std_logic;
    
            -- QPLL0 interface
            qpll0reset      : in std_logic;
            qpll0lock       : out std_logic;
            qpll0outclk     : out std_logic;
            qpll0refclk     : out std_logic;
            qpll0fblost     : out std_logic;
            qpll0reflost     : out std_logic;
    
            -- QPLL0 interface
            qpll1reset      : in std_logic;
            qpll1lock       : out std_logic;
            qpll1outclk     : out std_logic;
            qpll1refclk     : out std_logic;
            qpll1fblost     : out std_logic;
            qpll1reflost     : out std_logic
    
        );
    end entity gthe_common;
    
    architecture struct of gthe_common is
    
        ATTRIBUTE X_INTERFACE_INFO : STRING;
        ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
        ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
    
        signal gtrefclk : std_logic;
        signal gtrefclk_out2 : std_logic;
    
    
        component combpm_gtwizard_gthe4_common_wrapper
        port(
            GTHE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
            GTHE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
            GTHE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
            GTHE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
            GTHE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);