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Alexandre Moutardier Moutardier
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Aude Grabas grabas
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BENCE Aurelien
BENCE
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BRONES Romain
broucquart
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Diana Bachiller dbachiller
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ELAJJOURI ELAJJOURI
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HUBERT Nicolas HUBERT
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LABAT LABAT
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PEDEAU PEDEAU
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RICAUD Jean-Paul RICAUD
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SREEDHARAN Rajesh SREEDHARAN
- Feb 04, 2022
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BRONES Romain authoredVHDL * Add attributes on interface ports. * Bring back QPLL andCDR lock signals on the GT wrapper TCL * Add simple address map
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- Feb 03, 2022
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BRONES Romain authored
* Use a makefile to build the packaged IP
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- Feb 01, 2022
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BRONES Romain authored
* Corrections for synthesis * QPLL lock output signal TEMPORARY set to one !!
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- Jan 31, 2022
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BRONES Romain authored
* Use a package
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- Sep 24, 2021
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BRONES Romain authored
* Import sources from Cell Node initial project
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