- Mar 21, 2023
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BRONES Romain authored
* Also change the name of the table. * DESYRDL right shift the address by 2 before passing it to the memory. This is equivalent of having element of 32bits.
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- Mar 17, 2023
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BRONES Romain authored
* Remove undriven logic in protocol decoder.
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- Mar 09, 2023
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BRONES Romain authored
* Update doc with recent changes (Clock, filter) * Module ID is now hardcoded in RDL
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- Feb 02, 2023
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BRONES Romain authored
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BRONES Romain authored
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BRONES Romain authored
* Packet filter now uses DESYLIB true dual port RAM. * Add a packet filter before the module output. * Add packet filter as external memory in rdl.
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- Feb 01, 2023
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BRONES Romain authored
* One clock domain for AXI-MM * One for COM BPM logic * Xilinx CDC in between (control and status registers). * Also move component declaration in a package
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- Oct 05, 2022
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BRONES Romain authored
* Add a README proxy to doc/main.adoc * Include adoc generated by desyrdl for the register map. * Frame counters and rates were not linked to the addrmap. Fix that. * Add description for registers and fields in RDL
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- Oct 04, 2022
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BRONES Romain authored
* Change the naming in the package and HDL. * Complete and correct the doc.
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- Sep 07, 2022
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BRONES Romain authored
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- Aug 24, 2022
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BRONES Romain authored
* Also remove the ID field
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- Aug 18, 2022
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BRONES Romain authored
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- Aug 17, 2022
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BRONES Romain authored
* Update documentation * Top level uses bpmframe stream package * Remove unused files (quad common will be moved in application) * Capitalization killer for RDL file ;) * Change package version name, decomment the C_ID and C_Version for the AXI-MM registers.
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- Jun 22, 2022
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BRONES Romain authored
* Allow the possibility of counting above 65535
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- Apr 20, 2022
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BRONES Romain authored
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- Mar 21, 2022
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BRONES Romain authored
* Error detect can trigger an interrupt, a capture... * More debug to understand situations
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- Mar 18, 2022
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BRONES Romain authored
* Reset the register properly * Add register in memory map bank
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- Mar 14, 2022
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BRONES Romain authored
Top level: * Add MC time and PPS port * GT Interface ready combinatorial inside top level Protocol decoder * New GT Interface ready input port * New MC time and PPS input ports * New output ports for new features * Frame counters, frame rates * Sequence checkers * Change output AXIS packet : MC time, packet_time LSB only AXI interface: * Add registers for new features * Fix Makefile rule for RDL->VHD
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- Mar 03, 2022
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BRONES Romain authored
* Add debug ports of transceiver data and status before the protocole decoder. * Add a reset bit for PLL and datapath in AXI-MM interface.
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- Mar 01, 2022
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BRONES Romain authored
* Connect true QPLL lock bit * Attribute on QPLL_reset is now active high
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- Feb 16, 2022
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BRONES Romain authored
* Remove unused signals
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- Feb 15, 2022
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BRONES Romain authored
Also add Makefile rule to perform synthesis of IP bloc
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- Feb 14, 2022
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BRONES Romain authored
* GTHE COMMON must be outside IP (QPLL needed for other interfaces) * GTWizard created with TCL * GTWizard instantiated directly in top level
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- Feb 04, 2022
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BRONES Romain authored
VHDL * Add attributes on interface ports. * Bring back QPLL andCDR lock signals on the GT wrapper TCL * Add simple address map
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- Feb 03, 2022
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BRONES Romain authored
* Use a makefile to build the packaged IP
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- Feb 02, 2022
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BRONES Romain authored
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- Oct 04, 2021
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BRONES Romain authored
* Wrap the protocol bloc and the aximm control in a structural top level. * Get rid of the CDC, use only one clock. Domain crossing will be outside this bloc.
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