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  1. Mar 17, 2023
  2. Oct 04, 2022
  3. Aug 18, 2022
  4. Aug 17, 2022
  5. Jun 22, 2022
  6. Jun 21, 2022
  7. May 02, 2022
    • BRONES Romain's avatar
      VHDL fixes · 5e9a037b
      BRONES Romain authored
      Packet Filter
      * Address width for memory is now a generic
      * This width is a parameter for generation of xilinx ips
      * fix for synthesis
      
      COMBPM
      * use package for COMBPM packet
      
      package COMBPM
      * new constant for zero packet
      5e9a037b
  8. Mar 23, 2022
    • BRONES Romain's avatar
      Change CRC state machine · 5545f12e
      BRONES Romain authored
      * Do not allow to start CRC computation right after a result
      * CRC word counter up to 12 then roll over to 0
      5545f12e
  9. Mar 21, 2022
  10. Mar 18, 2022
  11. Mar 14, 2022
    • BRONES Romain's avatar
      Add features · 8c7670b6
      BRONES Romain authored
      Top level:
      * Add MC time and PPS port
      * GT Interface ready combinatorial inside top level
      
      Protocol decoder
      * New GT Interface ready input port
      * New MC time and PPS input ports
      * New output ports for new features
      * Frame counters, frame rates
      * Sequence checkers
      * Change output AXIS packet : MC time, packet_time LSB only
      
      AXI interface:
      * Add registers for new features
      * Fix Makefile rule for RDL->VHD
      8c7670b6
  12. Feb 16, 2022
  13. Oct 04, 2021
    • BRONES Romain's avatar
      Wrap in a top level · 9662d8e2
      BRONES Romain authored
      * Wrap the protocol bloc and the aximm control in a structural top
        level.
      * Get rid of the CDC, use only one clock. Domain crossing will be
        outside this bloc.
      9662d8e2
  14. Sep 24, 2021
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