* Remove undriven logic in protocol decoder.

* Change the naming in the package and HDL.
* Complete and correct the doc.

* Remove GT interface ready input: useless

* Allow the possibility of counting above 65535

* the y position received the x data :(

Packet Filter
* Address width for memory is now a generic
* This width is a parameter for generation of xilinx ips
* fix for synthesis

COMBPM
* use package for COMBPM packet

package COMBPM
* new constant for zero packet

* Do not allow to start CRC computation right after a result
* CRC word counter up to 12 then roll over to 0

* Need at least SOP and EOP.
* If any other flag is missing, raise error

* Reset the register properly
* Add register in memory map bank

Top level:
* Add MC time and PPS port
* GT Interface ready combinatorial inside top level

Protocol decoder
* New GT Interface ready input port
* New MC time and PPS input ports
* New output ports for new features
* Frame counters, frame rates
* Sequence checkers
* Change output AXIS packet : MC time, packet_time LSB only

AXI interface:
* Add registers for new features
* Fix Makefile rule for RDL->VHD

* Remove unused signals

* Wrap the protocol bloc and the aximm control in a structural top
  level.
* Get rid of the CDC, use only one clock. Domain crossing will be
  outside this bloc.

* Import sources from Cell Node initial project