- Mar 17, 2023
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BRONES Romain authored
* Remove undriven logic in protocol decoder.
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- Oct 04, 2022
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BRONES Romain authored
* Change the naming in the package and HDL. * Complete and correct the doc.
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- Aug 18, 2022
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BRONES Romain authored
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- Aug 17, 2022
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BRONES Romain authored
* Remove GT interface ready input: useless
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- Jun 22, 2022
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BRONES Romain authored
* Allow the possibility of counting above 65535
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- Jun 21, 2022
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BRONES Romain authored
* the y position received the x data :(
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- May 02, 2022
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BRONES Romain authored
Packet Filter * Address width for memory is now a generic * This width is a parameter for generation of xilinx ips * fix for synthesis COMBPM * use package for COMBPM packet package COMBPM * new constant for zero packet
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- Mar 23, 2022
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BRONES Romain authored
* Do not allow to start CRC computation right after a result * CRC word counter up to 12 then roll over to 0
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- Mar 21, 2022
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BRONES Romain authored
* Need at least SOP and EOP. * If any other flag is missing, raise error
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- Mar 18, 2022
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BRONES Romain authored
* Reset the register properly * Add register in memory map bank
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- Mar 14, 2022
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BRONES Romain authored
Top level: * Add MC time and PPS port * GT Interface ready combinatorial inside top level Protocol decoder * New GT Interface ready input port * New MC time and PPS input ports * New output ports for new features * Frame counters, frame rates * Sequence checkers * Change output AXIS packet : MC time, packet_time LSB only AXI interface: * Add registers for new features * Fix Makefile rule for RDL->VHD
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- Feb 16, 2022
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BRONES Romain authored
* Remove unused signals
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- Oct 04, 2021
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BRONES Romain authored
* Wrap the protocol bloc and the aximm control in a structural top level. * Get rid of the CDC, use only one clock. Domain crossing will be outside this bloc.
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- Sep 24, 2021
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BRONES Romain authored
* Import sources from Cell Node initial project
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