* for debug purpose

* Allow ID up to 255
* This changes dimension of memories, registers

* X and Y corrector controls are split
* Signed representation of coefficients

* The memory length depends on the serializer counter

* Matrix lines are numbered from 0 to 99
* X from 0 to 49 included, Y from 50 to 99 included

* Use DESYRDL specific property

* Two different register for enable and reset
* Duplicate coeffs
* Based on PSCID **table index**. > 50 is Y

* Threshold autostop is kept on both plane.
  Control moved to a dedicated register.
  When reached, stop both planes.

feat(average): Add orbit error and correction command moving average

fix(sim): Fiw simulation to match two correctors, add traces for moving
average

* Cast to signed

* No auto check !

* Update register address
* Configure second register as unitary

* Same generic bloc for operations
* Capture the stream of data and retains accumulator in memory
* Mirror memory for CPU readout

wip: initial commit

wip: Now a more generic bloc

wip: Add average tables to RDL

wip: integrate ma for oe in toplevel

wip: first corrections for simulation, alpha declared in package

wip: fixes for simulation

wip: fixes, secondary memory is smaller, no decimal part

wip: true rounding before wrinting to secondary memory

wip: Add average for PSC command

wip: fix sign extension on average orbit read

 Conflicts:
	hdl/top_corr_matrix.vhd

* Effective number of bit did not get over, but it is better to protect.

* typo: Enable bit also drove reset...
* use a NOR rather than a OR -> real thresh

* A simple threhshold comparator on data output.
* When Thresh is reached, disable correction (keep value).
* User can unlock the situation via control bits.
* Same threshold for all pscid.

*  Allows second order correction

* Add SUMSAT saturation
* Add first iteration with 0 in registers

* The corrector contains 4 coefficients that are enought to make a
  lag-compensator or lead-compensator
* Change the name of the block to erase "pi"
* Update the simulation data

!! Still error on simulation, to be fixed

* PSCID memory read require one clock tick, so add a pipeline stage
* To limit complexity, remove tready. Throttling will be done outside

* Change address with the new layout
* Add PSCID filling and checking

* This reads the memory in the proper order.

* This is handled better by DESYRDL

*  Instead of deriving ID field width

* Correction on testcase
* Add data source files
* update the python script that creates the data files

* Fix delay on matmul valid signal
* Fix length of validity for correction output

* Matmul coefs are now on 24 bits (23 effectives)
* Round more after matmul to keep result on 32b

All x then all y coefs

* Tie version register
* Import lib
* Copy data input before simulation

* There are always a couple of bits more on the address bus.
* Use a constant for data serializer ram

* This avoid a nasty bug in GHDL (LLVM backend) which doesn't work well
  with files with same names. We have another file named that way with
  DESYRDL.

* Also change the package constant declaration, add a few. All
  mathematic will be done outside of the package.