fix for external mem access from desyrdl record

* There are always a couple of bits more on the address bus.
* Use a constant for data serializer ram

hdl/data_serializer.vhd

@@ -42,7 +42,7 @@ architecture rtl of data_serializer is
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
-    signal cnt              : unsigned(pscid_table_i.addr'length-1 downto 0);
+    signal cnt              : unsigned(C_W_SER_CNT-1 downto 0);
     signal run_serial       : std_logic;
 
     signal pscid            : std_logic_vector(C_W_PSCID-1 downto 0);
@@ -118,14 +118,14 @@ begin
     -- Port A is read write from AXI controller, Port B is read only from logic
     inst_refx_table: entity desy.ram_tdp
     generic map(
-        G_ADDR      => pscid_table_i.addr'length,
+        G_ADDR      => C_W_SER_CNT,
         G_DATA      => C_W_PSCID
     )
     port map(
         pi_clk_a    => clk,
         pi_en_a     => pscid_table_i.en,
         pi_we_a     => pscid_table_i.we,
-        pi_addr_a   => pscid_table_i.addr,
+        pi_addr_a   => pscid_table_i.addr(C_W_SER_CNT-1 downto 0),
         pi_data_a   => pscid_table_i.data,
         po_data_a   => pscid_table_o.data,
         pi_clk_b    => clk,

hdl/matrix_mul.vhd

@@ -118,7 +118,7 @@ begin
     -- MATRIX MULTIPLICATION --
     ---------------------------
     -- Generate matrix line multiplication, two planes by loop iteration
-    G_MATRIX:for I in 0 to C_N_MM_PSC/2 generate
+    G_MATRIX:for I in 0 to C_N_MM_PSC/2-1 generate
         signal mult_x   : signed(C_W_MM_MULT-1 downto 0);
         signal mult_y   : signed(C_W_MM_MULT-1 downto 0);
         signal accu_x   : signed(C_W_MM_ACCU-1 downto 0);
@@ -140,7 +140,7 @@ begin
             pi_clk_a    => clk,
             pi_en_a     => mm_coef_i(2*I).en,
             pi_we_a     => mm_coef_i(2*I).we,
-            pi_addr_a   => mm_coef_i(2*I).addr,
+            pi_addr_a   => mm_coef_i(2*I).addr(C_W_MM_IDCNT-1 downto 0),
             pi_data_a   => mm_coef_i(2*I).data,
             po_data_a   => mm_coef_o(2*I).data,
             pi_clk_b    => clk,
@@ -160,7 +160,7 @@ begin
             pi_clk_a    => clk,
             pi_en_a     => mm_coef_i(2*I+1).en,
             pi_we_a     => mm_coef_i(2*I+1).we,
-            pi_addr_a   => mm_coef_i(2*I+1).addr,
+            pi_addr_a   => mm_coef_i(2*I+1).addr(C_W_MM_IDCNT-1 downto 0),
             pi_data_a   => mm_coef_i(2*I+1).data,
             po_data_a   => mm_coef_o(2*I+1).data,
             pi_clk_b    => clk,

hdl/orbit_error.vhd

@@ -76,7 +76,7 @@ begin
         pi_clk_a    => clk,
         pi_en_a     => reforbitx_i.en,
         pi_we_a     => reforbitx_i.we,
-        pi_addr_a   => reforbitx_i.addr,
+        pi_addr_a   => reforbitx_i.addr(C_W_BPMID-1 downto 0),
         pi_data_a   => reforbitx_i.data,
         po_data_a   => reforbitx_o.data,
         pi_clk_b    => clk,
@@ -96,7 +96,7 @@ begin
         pi_clk_a    => clk,
         pi_en_a     => reforbity_i.en,
         pi_we_a     => reforbity_i.we,
-        pi_addr_a   => reforbity_i.addr,
+        pi_addr_a   => reforbity_i.addr(C_W_BPMID-1 downto 0),
         pi_data_a   => reforbity_i.data,
         po_data_a   => reforbity_o.data,
         pi_clk_b    => clk,

hdl/pkg_corrmatrixpi.vhd

@@ -52,6 +52,9 @@ package pkg_corr_matrixpi is
 
     constant C_W_COR            : natural := 16; -- C_W_COR_SUM-C_N_COR_SAT-C_N_COR_RND
 
+    -- Serializer
+    constant C_W_SER_CNT        : natural := 7; -- natural(ceil(log2(real(C_N_MM_PSC))));
+
     ----------------------
     -- TYPE DECLARATION --
     ----------------------

rdl/corr_matrixpi.rdl

@@ -51,13 +51,13 @@ addrmap corr_matrixpi {
     mem {
         desc = "X Reference orbit.";
         memwidth = `C_W_BPMPOS;
-        mementries = `C_N_MM_BPM;
+        mementries = 2**`C_W_BPMID-1;
     } external REFORBITX;
 
     mem {
         desc = "Y Reference orbit.";
         memwidth = `C_W_BPMPOS;
-        mementries = `C_N_MM_BPM;
+        mementries = 2**`C_W_BPMID-1;
     } external REFORBITY;
 
     mem {