fix(sim): Change address, add PSCID test

* Change address with the new layout
* Add PSCID filling and checking

sim/tc_basic.vhd

@@ -103,16 +103,21 @@ begin
         for I in 0 to C_N_MM_BPM-1 loop
             readline(read_file, line_v);
             read(line_v, int_v);
-            Write(ManagerRec, f_addr(16#400#+I*4), f_sdata(int_v));
+            Write(ManagerRec, f_addr(16#200#+I*4), f_sdata(int_v));
         end loop;
         -- Y ref orbit
         for I in 0 to C_N_MM_BPM-1 loop
             readline(read_file, line_v);
             read(line_v, int_v);
-            Write(ManagerRec, f_addr(16#800#+I*4), f_sdata(int_v));
+            Write(ManagerRec, f_addr(16#400#+I*4), f_sdata(int_v));
         end loop;
         file_close(read_file);
 
+        log("+-- Writing PSCID...", INFO);
+        for J in 0 to C_N_MM_PSC-1 loop
+            Write(ManagerRec, f_addr(16#800#+J*4), f_sdata(J+1));
+        end loop;
+
         log("+-- Writing inv. resp. matrix coefficients...", INFO);
 
         -- Set Matrix Coefs
@@ -121,7 +126,7 @@ begin
             for I in 0 to C_N_MM_BPM-1 loop
                 readline(read_file, line_v);
                 read(line_v, int_v);
-                Write(ManagerRec, f_addr(16#E00#+J*512+I*4), f_sdata(int_v));
+                Write(ManagerRec, f_addr(16#C00#+J*512+I*4), f_sdata(int_v));
             end loop;
         end loop;
 
@@ -203,7 +208,7 @@ begin
 
                 read(line_v, int_v);
 
-                ExpData := std_logic_vector(to_unsigned(0, C_W_PSCID)) & std_logic_vector(to_signed(int_v, C_W_COR));
+                ExpData := std_logic_vector(to_unsigned(J+1, C_W_PSCID)) & std_logic_vector(to_signed(int_v, C_W_COR));
 
                 wait for 0 ns;
                 AffirmIfEqual(RxData, ExpData, "");