fix: declare constant

hdl/corr_ll.vhd

@@ -40,6 +40,7 @@ end entity corr_ll;
 
 architecture rtl of corr_ll is
 
+    constant C_N_A_RND  : natural := 8;
     constant C_DELAY    : natural := 5;
     type arr_slv is array (natural range <>) of std_logic_vector;
     signal delay_valid  : std_logic_vector(C_DELAY-1 downto 0);