* Use project properties for FPGA part
* Add packet filter to module
* Use packet version

* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.

* Add a gitignore to ignore the generated file.
* For now, this package has no use.

* Rename the RDL file, and the addrmap name to match the module name.
* Add addAddressSpace that gives the RDL file path.

* Put configuration in a variable to print it
* Put the quad_name in a variable, not fully used by now.
* Set the target FPGA in the TCL.

* Remove Makefile.
* Add tcl/main.tcl with mandatory functions.
* change tcl to create the GT wizard.