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BRONES Romain authored
* Add a gitignore to ignore the generated file. * For now, this package has no use.
BRONES Romain authored* Add a gitignore to ignore the generated file. * For now, this package has no use.
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main.tcl 1.65 KiB
################################################################################
# Main tcl for the module
################################################################################
# ==============================================================================
proc init {} {
# Configuration
# TODO Follow FWK
# variable quad_name
# set quad_name X0Y4
}
# ==============================================================================
proc setSources {} {
variable Vhdl
# Generate VHDL package with modle version
genModVerFile VHDL ../hdl/pkg_version.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../others/gthe_common.vhd
lappend Vhdl ../others/combpm_gtwizard_gthe4_common_wrapper.v
lappend Vhdl ../others/gtwizard_ultrascale_v1_7_gthe4_common.v
}
# ==============================================================================
proc setAddressSpace {} {
variable AddressSpace
addAddressSpace AddressSpace "COMBPM" RDL {} ../rdl/COMBPM.rdl
}
# ==============================================================================
proc doOnCreate {} {
variable Vhdl
addSources Vhdl
# TODO sould probably get that part number from the project configuration
set fpga_part "xczu11eg-ffvc1760-2L-e"
set_property part ${fpga_part} [current_project]
set_property target_language VHDL [current_project]
# Create GT wizard IP
source ../tcl/combpm_gtwizard.tcl
}
# ==============================================================================
proc doOnBuild {} {
}
# ==============================================================================
proc setSim {} {
}