* Update register address
* Configure second register as unitary

* Add SUMSAT saturation
* Add first iteration with 0 in registers

* The corrector contains 4 coefficients that are enought to make a
  lag-compensator or lead-compensator
* Change the name of the block to erase "pi"
* Update the simulation data

!! Still error on simulation, to be fixed

* PSCID memory read require one clock tick, so add a pipeline stage
* To limit complexity, remove tready. Throttling will be done outside

* Change address with the new layout
* Add PSCID filling and checking

* Correction on testcase
* Add data source files
* update the python script that creates the data files

* Tie version register
* Import lib
* Copy data input before simulation

* Also change the package constant declaration, add a few. All
  mathematic will be done outside of the package.