BRONES Romain
authored
* PSCID memory read require one clock tick, so add a pipeline stage * To limit complexity, remove tready. Throttling will be done outside
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| Name | Last commit | Last update |
|---|---|---|
| .. | ||
| TestCtrl_e.vhd | ||
| bpmdata.txt | ||
| corrout.txt | ||
| generate_datasim.py | ||
| reforbit.txt | ||
| respmat.txt | ||
| tb_corr_matrixpi.vhd | ||
| tc_basic.vhd | ||
| view1.gtkw | ||