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Commit f5ba74d6 authored by BRONES Romain's avatar BRONES Romain
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Multiple fixes for simulation

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hdl/corr_pi.vhd
+ 19
− 8
View file @ f5ba74d6
...@@ -22,6 +22,7 @@ entity corr_pi is ...@@ -22,6 +22,7 @@ entity corr_pi is
corr_ki : std_logic_vector(C_W_COR_KI-1 downto 0); corr_ki : std_logic_vector(C_W_COR_KI-1 downto 0);
reset_accu : in std_logic; reset_accu : in std_logic;
enable_accu : in std_logic;
enable_corr : in std_logic; enable_corr : in std_logic;
-- Corr output -- Corr output
...@@ -84,6 +85,7 @@ begin ...@@ -84,6 +85,7 @@ begin
signal ki_mult_rnd : signed(C_W_COR_MI-C_N_COR_MIRND-1 downto 0); signal ki_mult_rnd : signed(C_W_COR_MI-C_N_COR_MIRND-1 downto 0);
signal corr_sum : signed(C_W_COR_SUM-1 downto 0); signal corr_sum : signed(C_W_COR_SUM-1 downto 0);
signal corr_sum_rnd : signed(C_W_COR_SUM-C_N_COR_RND-1 downto 0); signal corr_sum_rnd : signed(C_W_COR_SUM-C_N_COR_RND-1 downto 0);
signal corr : signed(C_W_COR-1 downto 0);
begin begin
...@@ -94,7 +96,7 @@ begin ...@@ -94,7 +96,7 @@ begin
accu_post <= (others => '0'); accu_post <= (others => '0');
ki_mult <= (others => '0'); ki_mult <= (others => '0');
kp_mult <= (others => '0'); kp_mult <= (others => '0');
corrout <= (others => (others => '0')); corr <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
----------------- -----------------
...@@ -107,7 +109,7 @@ begin ...@@ -107,7 +109,7 @@ begin
if reset_accu = '1' then if reset_accu = '1' then
accu_post <= (others => '0'); accu_post <= (others => '0');
else else
if enable_corr = '1' then if enable_accu = '1' and matmult_valid = '1' then
accu_post <= f_sum_sat(f_sum_sat(accu_post, matmult(I)), accu_pre); accu_post <= f_sum_sat(f_sum_sat(accu_post, matmult(I)), accu_pre);
end if; end if;
end if; end if;
...@@ -121,10 +123,14 @@ begin ...@@ -121,10 +123,14 @@ begin
ki_mult <= accu_post * signed('0'&corr_ki); ki_mult <= accu_post * signed('0'&corr_ki);
kp_mult <= r_matmult * signed('0'&corr_kp); kp_mult <= r_matmult * signed('0'&corr_kp);
------------------------ ----------------------
-- FINAL MAP REGISTER -- -- FINAL SATURATION --
------------------------ ----------------------
corrout(I) <= f_resize_sat(corr_sum_rnd, C_W_COR); if enable_corr = '1' then
corr <= f_resize_sat(corr_sum_rnd, C_W_COR);
else
corr <= (others => '0');
end if;
end if; end if;
...@@ -146,8 +152,13 @@ begin ...@@ -146,8 +152,13 @@ begin
-------------------- --------------------
-- FINAL ROUNDING -- -- FINAL ROUNDING --
-------------------- --------------------
corr_sum_rnd <= corr_sum(C_W_COR_SUM-1 downto C_N_COR_RND) when corr_sum(C_N_COR_RND-1) = '1' else corr_sum_rnd <= f_resize_lsb(corr_sum, C_W_COR_SUM-C_N_COR_RND) when corr_sum(C_N_COR_RND-1) = '0' else
f_sum_sat(corr_sum(C_W_COR_SUM-1 downto C_N_COR_RND), to_signed(1,1)); f_sum_sat(f_resize_lsb(corr_sum, C_W_COR_SUM-C_N_COR_RND), to_signed(1,C_W_COR_SUM-C_N_COR_RND));
-------------
-- MAPPING --
-------------
corrout(I) <= corr;
end generate; end generate;
......
hdl/data_serializer.vhd
+ 1
− 1
View file @ f5ba74d6
...@@ -101,7 +101,7 @@ begin ...@@ -101,7 +101,7 @@ begin
elsif rising_edge(clk) then elsif rising_edge(clk) then
if run_serial = '1' then if run_serial = '1' then
if m_axis_tready = '1' then if m_axis_tready = '1' then
for I in 0 to C_N_MM_PSC-1 loop for I in 0 to C_N_MM_PSC-2 loop
r_corr(I) <= r_corr(I+1); r_corr(I) <= r_corr(I+1);
end loop; end loop;
end if; end if;
......
hdl/matrix_mul.vhd
+ 13
− 9
View file @ f5ba74d6
...@@ -46,7 +46,7 @@ architecture rtl of matrix_mul is ...@@ -46,7 +46,7 @@ architecture rtl of matrix_mul is
-- delay registers -- delay registers
signal r_pos_x : signed(pos_x'left downto 0); signal r_pos_x : signed(pos_x'left downto 0);
signal r_pos_y : signed(pos_y'left downto 0); signal r_pos_y : signed(pos_y'left downto 0);
signal r_seq : arr_slv(0 to 3)(C_W_BPMSEQ-1 downto 0); signal r_seq : std_logic_vector(C_W_BPMSEQ-1 downto 0);
signal r_tvalid : std_logic_vector(3 downto 0); signal r_tvalid : std_logic_vector(3 downto 0);
...@@ -57,6 +57,7 @@ architecture rtl of matrix_mul is ...@@ -57,6 +57,7 @@ architecture rtl of matrix_mul is
signal id_cnt : unsigned(C_W_MM_IDCNT-1 downto 0); signal id_cnt : unsigned(C_W_MM_IDCNT-1 downto 0);
signal new_seq : std_logic; signal new_seq : std_logic;
signal mul_done : std_logic;
begin begin
...@@ -70,16 +71,15 @@ begin ...@@ -70,16 +71,15 @@ begin
if rst_n = '0' then if rst_n = '0' then
r_pos_x <= (others => '0'); r_pos_x <= (others => '0');
r_pos_y <= (others => '0'); r_pos_y <= (others => '0');
r_seq <= (others => (others => '0')); r_seq <= (others => '1');
r_tvalid <= (others => '0'); r_tvalid <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
r_pos_x <= pos_x; r_pos_x <= pos_x;
r_pos_y <= pos_y; r_pos_y <= pos_y;
r_seq(0) <= pos_seq; if pos_tvalid = '1' then
for I in 1 to r_seq'right loop r_seq <= pos_seq;
r_seq(I) <= r_seq(I-1); end if;
end loop;
r_tvalid <= r_tvalid(r_tvalid'left-1 downto 0) & pos_tvalid; r_tvalid <= r_tvalid(r_tvalid'left-1 downto 0) & pos_tvalid;
end if; end if;
...@@ -90,7 +90,8 @@ begin ...@@ -90,7 +90,8 @@ begin
---------------- ----------------
-- SEQ DETECT -- -- SEQ DETECT --
---------------- ----------------
new_seq <= '1' when pos_seq /= r_seq(0) else '0'; new_seq <= pos_tvalid when pos_seq /= r_seq else '0';
rst_accu <= new_seq;
---------------- ----------------
-- ID COUNTER -- -- ID COUNTER --
...@@ -99,10 +100,13 @@ begin ...@@ -99,10 +100,13 @@ begin
begin begin
if rst_n = '0' then if rst_n = '0' then
id_cnt <= (others => '1'); id_cnt <= (others => '1');
mul_done <= '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
if id_cnt = 0 then if id_cnt = 0 then
id_cnt <= unsigned(id_cnt_load); id_cnt <= unsigned(id_cnt_load);
mul_done <= '1';
else else
mul_done <= '0';
if new_seq= '1' then if new_seq= '1' then
id_cnt <= unsigned(id_cnt_load); id_cnt <= unsigned(id_cnt_load);
else else
...@@ -213,7 +217,7 @@ begin ...@@ -213,7 +217,7 @@ begin
-------------------- --------------------
-- OUTPUT CONNECT -- -- OUTPUT CONNECT --
-------------------- --------------------
matmult_tvalid <= r_tvalid(3); matmult_tvalid <= mul_done;
matmult_seq <= r_seq(3); matmult_seq <= r_seq;
end architecture; end architecture;
hdl/orbit_error.vhd
+ 5
− 0
View file @ f5ba74d6
...@@ -130,6 +130,8 @@ begin ...@@ -130,6 +130,8 @@ begin
r_bpm_id <= (others => (others => '0')); r_bpm_id <= (others => (others => '0'));
r_bpm_seq <= (others => (others => '0')); r_bpm_seq <= (others => (others => '0'));
r_tvalid <= (others => '0'); r_tvalid <= (others => '0');
r_bpm_x <= (others => '0');
r_bpm_y <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
r_bpm_id(0) <= bpm_id; r_bpm_id(0) <= bpm_id;
for I in 1 to r_bpm_id'right loop for I in 1 to r_bpm_id'right loop
...@@ -141,6 +143,9 @@ begin ...@@ -141,6 +143,9 @@ begin
r_bpm_seq(I) <= r_bpm_seq(I-1); r_bpm_seq(I) <= r_bpm_seq(I-1);
end loop; end loop;
r_bpm_x <= bpm_x;
r_bpm_y <= bpm_y;
r_tvalid <= r_tvalid(r_tvalid'left-1 downto 0) & bpm_tvalid; r_tvalid <= r_tvalid(r_tvalid'left-1 downto 0) & bpm_tvalid;
end if; end if;
end process; end process;
......
hdl/pkg_corrmatrixpi.vhd
+ 8
− 8
View file @ f5ba74d6
...@@ -37,18 +37,18 @@ package pkg_corr_matrixpi is ...@@ -37,18 +37,18 @@ package pkg_corr_matrixpi is
constant C_W_MM : natural := 32; --C_W_MM_ACCU-C_N_MM_SAT-C_N_MM_RND constant C_W_MM : natural := 32; --C_W_MM_ACCU-C_N_MM_SAT-C_N_MM_RND
-- PI corrector -- PI corrector
constant C_W_COR_KP : natural := 18; constant C_W_COR_KP : natural := 17;
constant C_W_COR_KI : natural := 18; constant C_W_COR_KI : natural := 17;
constant C_W_COR_ACCU : natural := 40; --C_W_MM+...; constant C_W_COR_ACCU : natural := 40; --C_W_MM+ ?to choose?
constant C_W_COR_MP : natural := 40; --C_W_MM+C_W_COR_KP constant C_W_COR_MP : natural := 50; --C_W_MM+C_W_COR_KP+1
constant C_W_COR_MI : natural := 58; --C_W_COR_ACCU+C_W_COR_KI constant C_W_COR_MI : natural := 58; --C_W_COR_ACCU+C_W_COR_KI+1
constant C_N_COR_MIRND : natural := 18; constant C_N_COR_MIRND : natural := 8;
constant C_W_COR_SUM : natural := 40; -- max(C_W_COR_MP,C_W_COR_MI-C_N_COR_MIRND) constant C_W_COR_SUM : natural := 50; -- max(C_W_COR_MP,C_W_COR_MI-C_N_COR_MIRND)
constant C_N_COR_SAT : natural := 0; constant C_N_COR_SAT : natural := 0;
constant C_N_COR_RND : natural := 24; constant C_N_COR_RND : natural := 34;
constant C_W_COR : natural := 16; -- C_W_COR_SUM-C_N_COR_SAT-C_N_COR_RND constant C_W_COR : natural := 16; -- C_W_COR_SUM-C_N_COR_SAT-C_N_COR_RND
......
hdl/top_corr_matrixpi.vhd
+ 2
− 1
View file @ f5ba74d6
...@@ -169,7 +169,8 @@ begin ...@@ -169,7 +169,8 @@ begin
corr_ki => mm_a2l.CORR_KI.data.data, corr_ki => mm_a2l.CORR_KI.data.data,
reset_accu => mm_a2l.CONTROL.RST_ACC.data(0), reset_accu => mm_a2l.CONTROL.RST_ACC.data(0),
enable_corr => mm_a2l.CONTROL.ENABLE.data(0), enable_accu => mm_a2l.CONTROL.ENABLE_ACCU.data(0),
enable_corr => mm_a2l.CONTROL.ENABLE_CORR.data(0),
-- Corr output -- Corr output
corrout_valid => corrout_valid, corrout_valid => corrout_valid,
......
rdl/corr_matrixpi.rdl
+ 6
− 5
View file @ f5ba74d6
...@@ -29,8 +29,9 @@ addrmap corr_matrixpi { ...@@ -29,8 +29,9 @@ addrmap corr_matrixpi {
reg { reg {
desc="Global control of the corrector."; desc="Global control of the corrector.";
field {sw = rw; hw = r;} ENABLE; field {sw = rw; hw = r;} ENABLE_CORR;
field {sw = rw; hw = r;} RST_ACC; field {sw = rw; hw = r;} RST_ACC;
field {sw = rw; hw = r;} ENABLE_ACCU;
} CONTROL; } CONTROL;
reg { reg {
...@@ -45,19 +46,19 @@ addrmap corr_matrixpi { ...@@ -45,19 +46,19 @@ addrmap corr_matrixpi {
reg { reg {
desc="Number of ID to count for matrix multiplication."; desc="Number of ID to count for matrix multiplication.";
field {sw = rw; hw = r;} data[`C_W_MM_IDCNT] = `C_N_MM_BPM-1; field {sw = rw; hw = r;} data[`C_W_MM_IDCNT] = `C_N_MM_BPM;
} MM_ID_CNT; } MM_ID_CNT;
mem { mem {
desc = "X Reference orbit."; desc = "X Reference orbit.";
memwidth = `C_W_BPMPOS; memwidth = `C_W_BPMPOS;
mementries = 2**`C_W_BPMID-1; mementries = 2**`C_W_BPMID;
} external REFORBITX; } external REFORBITX;
mem { mem {
desc = "Y Reference orbit."; desc = "Y Reference orbit.";
memwidth = `C_W_BPMPOS; memwidth = `C_W_BPMPOS;
mementries = 2**`C_W_BPMID-1; mementries = 2**`C_W_BPMID;
} external REFORBITY; } external REFORBITY;
mem { mem {
...@@ -70,7 +71,7 @@ addrmap corr_matrixpi { ...@@ -70,7 +71,7 @@ addrmap corr_matrixpi {
mem { mem {
desc = "Matrix multiplication coefficients."; desc = "Matrix multiplication coefficients.";
memwidth = `C_W_MM_COEF; memwidth = `C_W_MM_COEF;
mementries = `C_N_MM_BPM; mementries = 2**`C_W_MM_IDCNT;
} external MATRIXCOEF[`C_N_MM_PSC]; } external MATRIXCOEF[`C_N_MM_PSC];
}; };
......
sim/tb_corr_matrixpi.vhd
+ 2
− 1
View file @ f5ba74d6
...@@ -20,7 +20,7 @@ end entity tb_corr_matrixpi; ...@@ -20,7 +20,7 @@ end entity tb_corr_matrixpi;
architecture TestHarness of tb_corr_matrixpi is architecture TestHarness of tb_corr_matrixpi is
constant TPERIOD_CLK : time := 4 ns ; constant TPERIOD_CLK : time := 10 ns ;
constant TPD : time := 1 ns ; constant TPD : time := 1 ns ;
...@@ -210,6 +210,7 @@ begin ...@@ -210,6 +210,7 @@ begin
-- Testbench Transaction Interface -- Testbench Transaction Interface
TransRec => StreamTxRec TransRec => StreamTxRec
); );
tb_axis_tx_tready <= '1'; -- We do not have a TREADY on DUT
-- Axi-Stream Verification Manager -- Axi-Stream Verification Manager
vc_axis_receiver : AxiStreamReceiver vc_axis_receiver : AxiStreamReceiver
......
sim/tc_basic.vhd
+ 31
− 11
View file @ f5ba74d6
...@@ -22,6 +22,11 @@ architecture basic of TestCtrl is ...@@ -22,6 +22,11 @@ architecture basic of TestCtrl is
return std_logic_vector(to_signed(data, AXI_DATA_WIDTH)); return std_logic_vector(to_signed(data, AXI_DATA_WIDTH));
end function; end function;
function f_data(data:natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(data, AXI_DATA_WIDTH));
end function;
function f_bpmpkt(id:natural; x:integer; y:integer) return std_logic_vector is function f_bpmpkt(id:natural; x:integer; y:integer) return std_logic_vector is
begin begin
return std_logic_vector(to_unsigned(id, C_W_BPMID)) & std_logic_vector(to_signed(x, C_W_BPMPOS)) & std_logic_vector(to_signed(y, C_W_BPMPOS)); return std_logic_vector(to_unsigned(id, C_W_BPMID)) & std_logic_vector(to_signed(x, C_W_BPMPOS)) & std_logic_vector(to_signed(y, C_W_BPMPOS));
...@@ -74,18 +79,33 @@ begin ...@@ -74,18 +79,33 @@ begin
WaitForClock(ManagerRec, 2); WaitForClock(ManagerRec, 2);
log("Read version", INFO) ; log("Read version", INFO) ;
Read(ManagerRec, f_addr(0), Data) ; Read(ManagerRec, f_addr(4), Data) ;
AffirmIfEqual(Data, C_VERSION, "Manager Read Data: ") ; AffirmIfEqual(Data, C_VERSION, "Manager Read Data: ") ;
log("==--- Configure the DUT ---==", INFO); log("==--- Configure the DUT ---==", INFO);
log("+-- Global Config", INFO); log("+-- Global Config", INFO);
-- Correction coefficients -- Correction coefficients
Write(ManagerRec, f_addr(12), f_sdata(2387)); Write(ManagerRec, f_addr(12), f_data(16#0000E641#));
Write(ManagerRec, f_addr(16), f_sdata(7353)); Write(ManagerRec, f_addr(16), f_data(16#000083B2#));
-- Enable
Write(ManagerRec, f_addr(8), f_sdata(5));
-- Set all orbit reference to 0 -- Set all orbit reference to 0
for I in 0 to C_N_MM_BPM-1 loop for I in 0 to C_N_MM_BPM-1 loop
Write(ManagerRec, f_addr(20+I*4), f_sdata(0)); --Write(ManagerRec, f_addr(16#400#+I*4), f_sdata(0));
--Write(ManagerRec, f_addr(16#800#+I*4), f_sdata(0));
end loop;
-- Set Matrix Coefs, diagonal
for I in 0 to C_N_MM_BPM-1 loop
for J in 0 to C_N_MM_PSC-1 loop
if I = J then
Write(ManagerRec, f_addr(16#E00#+I*512+J*4), f_sdata(32768));
else
--Write(ManagerRec, f_addr(16#E00#+I*512+J*4), f_sdata(0));
end if;
end loop;
end loop; end loop;
WaitForBarrier(ConfigDone); WaitForBarrier(ConfigDone);
...@@ -94,9 +114,6 @@ begin ...@@ -94,9 +114,6 @@ begin
WaitForClock(ManagerRec, 10) ; WaitForClock(ManagerRec, 10) ;
--Write(ManagerRec, std_logic_vector(C_REGISTER_INFO(C_CONFIG_ID).address), X"00000001") ; --Write(ManagerRec, std_logic_vector(C_REGISTER_INFO(C_CONFIG_ID).address), X"00000001") ;
-- Wait for outputs to propagate and signal TestDone
WaitForClock(ManagerRec, 2000) ;
WaitForBarrier(TestDone) ;
wait ; wait ;
end process ManagerProc ; end process ManagerProc ;
...@@ -119,12 +136,15 @@ begin ...@@ -119,12 +136,15 @@ begin
WaitForBarrier(ConfigDone) ; WaitForBarrier(ConfigDone) ;
log("Sending bpm packets", INFO); log("Sending bpm packets", INFO);
for NTURN in 0 to 3 loop
for I in 3 to 124 loop for I in 3 to 124 loop
Send(StreamTxRec, f_bpmpkt(I, -7874+333*I, 5679-1098*I)); Send(StreamTxRec, f_bpmpkt(I, -457874+3833*I, 125679-81098*I), std_logic_vector(to_unsigned(NTURN,8)&'0'));
end loop;
-- Simulate interpacket delay
WaitForClock(StreamTxRec, 150) ;
end loop; end loop;
-- Wait for outputs to propagate and signal TestDone
WaitForClock(StreamTxRec, 2) ;
WaitForBarrier(TestDone) ; WaitForBarrier(TestDone) ;
wait ; wait ;
end process TransmitterProc ; end process TransmitterProc ;
......
sim/view1.gtkw 0 → 100644
+ 92
− 0
View file @ f5ba74d6
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