Skip to content
Snippets Groups Projects

Compare revisions

Changes are shown as if the source revision was being merged into the target revision. Learn more about comparing revisions.

Source

Select target project
No results found
Select Git revision
  • dev
  • feat-merge-filter
  • fix
  • integrate
  • master
  • to_fwk
  • 1.1.0
  • 1.1.1
  • 1.2
  • 1.2.1
  • 1.3
11 results

Target

Select target project
  • dg/fofb/com_bpm
1 result
Select Git revision
Loading items
Show changes
Commits on Source (4)
library ieee; library ieee;
use ieee.std_logic_1164.all; USe ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.pkg_bpmpacket_stream.all;
library desy; library desy;
use desy.ram_tdp; use desy.ram_tdp;
use work.pkg_combpm.C_W_BPMID;
use work.pkg_combpm.C_W_TDEST;
entity combpm_packet_filter is entity combpm_packet_filter is
generic( generic(
G_W_ADDR_TABLE : natural G_W_ADDR_TABLE : natural;
G_W_TDATA : natural
); );
port( port(
axis_clk : in std_logic; axis_clk : in std_logic;
...@@ -17,14 +20,14 @@ entity combpm_packet_filter is ...@@ -17,14 +20,14 @@ entity combpm_packet_filter is
axis_rst_n : in std_logic; axis_rst_n : in std_logic;
-- AXIS SLAVE INTERFACE -- AXIS SLAVE INTERFACE
s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0);
s_axis_tdata : in std_logic_vector(C_TDATA_W-1 downto 0);
s_axis_tvalid : in std_logic; s_axis_tvalid : in std_logic;
s_axis_tdata : in std_logic_vector(G_W_TDATA-1 downto 0);
s_axis_tuser_bpmid : in std_logic_vector(C_W_BPMID-1 downto 0);
-- AXIS MASTER INTERFACE -- AXIS MASTER INTERFACE
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0);
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0);
m_axis_tvalid : out std_logic; m_axis_tvalid : out std_logic;
m_axis_tdata : out std_logic_vector(G_W_TDATA-1 downto 0);
m_axis_tdest : out std_logic_vector(C_W_TDEST-1 downto 0);
-- Table configuration interface -- Table configuration interface
pi_table_en : in std_logic; pi_table_en : in std_logic;
...@@ -42,37 +45,38 @@ architecture rtl of combpm_packet_filter is ...@@ -42,37 +45,38 @@ architecture rtl of combpm_packet_filter is
------------------------ ------------------------
-- SIGNAL DECLARATION -- -- SIGNAL DECLARATION --
------------------------ ------------------------
signal in_packet : t_bpmpacket; signal r1_tdata : std_logic_vector(G_W_TDATA-1 downto 0);
signal out_packet : t_bpmpacket; signal r2_tdata : std_logic_vector(G_W_TDATA-1 downto 0);
signal r_bpmid : std_logic_vector(C_W_BPMID-1 downto 0);
signal table_data : std_logic_vector(7 downto 0); signal table_data : std_logic_vector(7 downto 0);
signal tvalid_r : std_logic_vector(1 downto 0); signal tvalid_r : std_logic_vector(1 downto 0);
signal zero_packet : std_logic_vector(C_TDATA_W-1 downto 0);
begin begin
zero_packet <= (others => '0');
---------------------- ----------------------
-- STREAM REGISTERS -- -- STREAM REGISTERS --
---------------------- ----------------------
p_main: process(axis_clk, axis_rst_n) p_main: process(axis_clk, axis_rst_n)
begin begin
if axis_rst_n = '0' then if axis_rst_n = '0' then
in_packet <= slv2bpmpacket(zero_packet); r1_tdata <= (others => '0');
out_packet <= slv2bpmpacket(zero_packet); r2_tdata <= (others => '0');
r_bpmid <= (others => '0');
tvalid_r <= (others => '0');
elsif rising_edge(axis_clk) then elsif rising_edge(axis_clk) then
-- Register input packet -- Register input packet
if s_axis_tvalid = '1' then if s_axis_tvalid = '1' then
in_packet <= slv2bpmpacket(s_axis_tdata); r1_tdata <= s_axis_tdata;
r_bpmid <= s_axis_tuser_bpmid;
end if; end if;
tvalid_r(tvalid_r'left downto 1) <= tvalid_r(tvalid_r'left-1 downto 0); tvalid_r(tvalid_r'left downto 1) <= tvalid_r(tvalid_r'left-1 downto 0);
tvalid_r(0) <= s_axis_tvalid; tvalid_r(0) <= s_axis_tvalid;
out_packet <= in_packet; r2_tdata <= r1_tdata;
end if; end if;
end process; end process;
...@@ -80,8 +84,8 @@ begin ...@@ -80,8 +84,8 @@ begin
----------------- -----------------
-- AXIS OUTPUT -- -- AXIS OUTPUT --
----------------- -----------------
m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W)); m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_W_TDEST));
m_axis_tdata <= bpmpacket2slv(out_packet); m_axis_tdata <= r2_tdata;
m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7); m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7);
------------------ ------------------
...@@ -103,7 +107,7 @@ begin ...@@ -103,7 +107,7 @@ begin
pi_clk_b => axis_clk, pi_clk_b => axis_clk,
pi_en_b => '1', pi_en_b => '1',
pi_we_b => '0', pi_we_b => '0',
pi_addr_b => in_packet.bpm_id(G_W_ADDR_TABLE-1 downto 0), pi_addr_b => r_bpmid(G_W_ADDR_TABLE-1 downto 0),
pi_data_b => (others => '0'), pi_data_b => (others => '0'),
po_data_b => table_data po_data_b => table_data
); );
......
...@@ -3,7 +3,7 @@ library ieee; ...@@ -3,7 +3,7 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.pkg_bpmpacket_stream.all; use work.pkg_combpm.all;
entity combpm_protocol_electron is entity combpm_protocol_electron is
port( port(
...@@ -17,10 +17,16 @@ entity combpm_protocol_electron is ...@@ -17,10 +17,16 @@ entity combpm_protocol_electron is
gt_datarx : in std_logic_vector(15 downto 0); -- Deserialized data. gt_datarx : in std_logic_vector(15 downto 0); -- Deserialized data.
-- AXIS interface -- AXIS interface
m_axis_m2s : out t_bpmpacket_axis_m2s; m_axis_tvalid : out std_logic;
m_axis_tdata_posx : out std_logic_vector(C_W_POS-1 downto 0);
m_axis_tdata_posy : out std_logic_vector(C_W_POS-1 downto 0);
m_axis_tdata_bpmid : out std_logic_vector(C_W_BPMID-1 downto 0);
m_axis_tdata_faseq : out std_logic_vector(C_W_SEQ-1 downto 0);
m_axis_tuser_mcts : out std_logic_vector(C_W_MCTS-1 downto 0);
-- Status and control interface -- Status and control interface
soft_reset : in std_logic; -- Reset all counters. soft_reset : in std_logic; -- Reset all counters.
seq_offset : in signed(15 downto 0); -- Sequence numbering offset
frame_seq_cnt : out std_logic_vector(15 downto 0); -- Number of frame in last sequence. frame_seq_cnt : out std_logic_vector(15 downto 0); -- Number of frame in last sequence.
frame_valid_cnt : out std_logic_vector(31 downto 0); -- Count of valid frames. frame_valid_cnt : out std_logic_vector(31 downto 0); -- Count of valid frames.
frame_invalid_cnt : out std_logic_vector(31 downto 0); -- Count of invalid frames. frame_invalid_cnt : out std_logic_vector(31 downto 0); -- Count of invalid frames.
...@@ -82,8 +88,7 @@ architecture rtl of combpm_protocol_electron is ...@@ -82,8 +88,7 @@ architecture rtl of combpm_protocol_electron is
signal rate_valid_r : unsigned(31 downto 0); signal rate_valid_r : unsigned(31 downto 0);
signal rate_invalid_r : unsigned(31 downto 0); signal rate_invalid_r : unsigned(31 downto 0);
signal packet : t_bpmpacket; signal axis_tvalid : std_logic;
signal m_axi_tvalid : std_logic;
signal cnt_seq_mismatch : std_logic; signal cnt_seq_mismatch : std_logic;
signal seq_discontinuity : std_logic; signal seq_discontinuity : std_logic;
...@@ -270,32 +275,30 @@ begin ...@@ -270,32 +275,30 @@ begin
-------------- --------------
-- AXIS OUT -- -- AXIS OUT --
-------------- --------------
m_axis_m2s.tdest <= (others => '0');
m_axis_m2s.tdata <= bpmpacket2slv(packet);
m_axis_m2s.tlast <= '1'; -- One transfer is One packet.
m_axis_m2s.tvalid <= m_axi_tvalid;
p_axis:process(clk, rst_n) p_axis:process(clk, rst_n)
begin begin
if rst_n = '0' then if rst_n = '0' then
packet <= C_BPMPACKET_ZERO; m_axis_tvalid <= '0';
m_axi_tvalid <= '0'; m_axis_tdata_posx <= (others => '0');
m_axis_tdata_posy <= (others => '0');
m_axis_tdata_bpmid <= (others => '0');
m_axis_tuser_mcts <= (others => '0');
m_axis_tdata_faseq <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
if flag_all = '1' then if flag_all = '1' then
-- Make AXIS packet -- Make AXIS packet
packet.pos_x <= packet_xpos; m_axis_tdata_posx <= packet_xpos;
packet.pos_y <= packet_ypos; m_axis_tdata_posy <= packet_ypos;
packet.bpm_id <= "000000" & packet_bpmid; m_axis_tdata_bpmid <= "000000" & packet_bpmid;
packet.mc_timestamp <= mc_time; m_axis_tuser_mcts <= mc_time;
packet.fa_seq <= packet_timestamp(7 downto 0); m_axis_tdata_faseq <= std_logic_vector(signed(packet_timestamp)+seq_offset);
-- AXIS TVALID -- AXIS TVALID
m_axi_tvalid <= not soft_reset; m_axis_tvalid <= not soft_reset;
else else
m_axi_tvalid <= '0'; m_axis_tvalid <= '0';
end if; end if;
end if; end if;
end process p_axis; end process p_axis;
......
-- Package BPMPACKET STREAM
-- this package describe the format of the AXI-Stream interface used by blocs of the module COMBPM.
--
-- The usefull things are :
-- * Two record types for port interfaces: t_bpmpacket_axis_m2s and t_bpmpacket_axis_s2m.
-- * One record type for frame fields: t_bpmpacket.
-- * Two functions to transform TDATA (std_logic_vector) to/from t_bpmpacket: slv2bpmpacket and bpmpacket2slv.
library ieee;
use ieee.std_logic_1164.all;
package pkg_bpmpacket_stream is
----------------------
-- MACRO PARAMETERS --
----------------------
constant C_TDEST_W : natural := 7;
constant C_TDATA_W : natural := 128;
---------------------------------
-- AXIS MASTER/SLAVE INTERFACE --
---------------------------------
type t_bpmpacket_axis_m2s is record
tdest : std_logic_vector(C_TDEST_W-1 downto 0);
tdata : std_logic_vector(C_TDATA_W-1 downto 0);
tlast : std_logic;
tvalid : std_logic;
end record t_bpmpacket_axis_m2s;
type t_bpmpacket_axis_s2m is record
tready : std_logic;
end record t_bpmpacket_axis_s2m;
------------------------
-- AXIS STREAM PACKET --
------------------------
type t_bpmpacket is record
pos_x : std_logic_vector(31 downto 0);
pos_y : std_logic_vector(31 downto 0);
bpm_id : std_logic_vector(15 downto 0);
mc_timestamp : std_logic_vector(39 downto 0);
fa_seq : std_logic_vector(7 downto 0);
end record t_bpmpacket;
constant C_BPMPACKET_ZERO : t_bpmpacket := (
pos_x => (others => '0'),
pos_y => (others => '0'),
bpm_id => (others => '0'),
mc_timestamp => (others => '0'),
fa_seq => (others => '0')
);
function slv2bpmpacket(
signal tdata : std_logic_vector(C_TDATA_W-1 downto 0)
)
return t_bpmpacket;
function bpmpacket2slv(
signal packet : t_bpmpacket
)
return std_logic_vector;
end package;
package body pkg_bpmpacket_stream is
function slv2bpmpacket(
signal tdata : std_logic_vector(C_TDATA_W-1 downto 0)
)
return t_bpmpacket is
variable packet : t_bpmpacket;
begin
packet.pos_x := tdata(31 downto 0);
packet.pos_y := tdata(63 downto 32);
packet.bpm_id := tdata(79 downto 64);
packet.mc_timestamp := tdata(119 downto 80);
packet.fa_seq := tdata(127 downto 120);
return packet;
end function;
function bpmpacket2slv(
signal packet : t_bpmpacket
)
return std_logic_vector is
begin
return packet.fa_seq & packet.mc_timestamp & packet.bpm_id & packet.pos_y & packet.pos_x;
end function;
end package body;
...@@ -9,6 +9,11 @@ package pkg_combpm is ...@@ -9,6 +9,11 @@ package pkg_combpm is
constant C_W_ADDR_TABLE : natural := 8; constant C_W_ADDR_TABLE : natural := 8;
constant C_W_TDEST : natural := 7;
constant C_W_POS : natural := 32;
constant C_W_BPMID : natural := 16;
constant C_W_SEQ : natural := 16;
constant C_W_MCTS : natural := 40;
------------------------- -------------------------
-- GT WIZARD COMPONENT -- -- GT WIZARD COMPONENT --
......
...@@ -13,7 +13,6 @@ library desyrdl; ...@@ -13,7 +13,6 @@ library desyrdl;
use desyrdl.common.all; use desyrdl.common.all;
use desyrdl.pkg_combpm.all; use desyrdl.pkg_combpm.all;
use work.pkg_bpmpacket_stream.all;
use work.pkg_combpm_version.all; use work.pkg_combpm_version.all;
use work.pkg_combpm.all; use work.pkg_combpm.all;
...@@ -48,8 +47,11 @@ entity top_combpm_electron is ...@@ -48,8 +47,11 @@ entity top_combpm_electron is
-- AXIS interface -- AXIS interface
m_axis_aclk : out std_logic; m_axis_aclk : out std_logic;
m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0); m_axis_tdata_posx : out std_logic_vector(C_W_POS-1 downto 0);
m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0); m_axis_tdata_posy : out std_logic_vector(C_W_POS-1 downto 0);
m_axis_tdata_bpmid : out std_logic_vector(C_W_BPMID-1 downto 0);
m_axis_tdata_seq : out std_logic_vector(C_W_SEQ-1 downto 0);
m_axis_tdest : out std_logic_vector(C_W_TDEST-1 downto 0);
m_axis_tvalid : out std_logic; m_axis_tvalid : out std_logic;
-- AXI bus interface -- AXI bus interface
...@@ -97,7 +99,14 @@ architecture struct of top_combpm_electron is ...@@ -97,7 +99,14 @@ architecture struct of top_combpm_electron is
signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side
signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side
signal m_axis_decoded_m2s : t_bpmpacket_axis_m2s; signal m_axis_decoded_tvalid : std_logic;
signal m_axis_decoded_tdata : std_logic_vector(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto 0);
signal m_axis_decoded_tdata_posx : std_logic_vector(C_W_POS-1 downto 0);
signal m_axis_decoded_tdata_posy : std_logic_vector(C_W_POS-1 downto 0);
signal m_axis_decoded_tdata_bpmid : std_logic_vector(C_W_BPMID-1 downto 0);
signal m_axis_decoded_tdata_faseq : std_logic_vector(C_W_SEQ-1 downto 0);
signal m_axis_filt_tdata : std_logic_vector(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto 0);
begin begin
...@@ -253,10 +262,16 @@ begin ...@@ -253,10 +262,16 @@ begin
pps => pps_resync, pps => pps_resync,
gt_datarx => gt_datarx, gt_datarx => gt_datarx,
m_axis_m2s => m_axis_decoded_m2s, m_axis_tvalid => m_axis_decoded_tvalid,
m_axis_tdata_posx => m_axis_decoded_tdata_posx,
m_axis_tdata_posy => m_axis_decoded_tdata_posy,
m_axis_tdata_bpmid => m_axis_decoded_tdata_bpmid,
m_axis_tdata_faseq => m_axis_decoded_tdata_faseq,
m_axis_tuser_mcts => open,
mc_time => mc_time, mc_time => mc_time,
soft_reset => addrmap_r.RESET.SOFTRESET.data(0), soft_reset => addrmap_r.RESET.SOFTRESET.data(0),
seq_offset => signed(addrmap_r.SEQ_OFFSET.data.data),
frame_seq_cnt => frame_seq_cnt, frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt, frame_valid_cnt => frame_valid_cnt,
frame_invalid_cnt => frame_invalid_cnt, frame_invalid_cnt => frame_invalid_cnt,
...@@ -268,6 +283,10 @@ begin ...@@ -268,6 +283,10 @@ begin
flag_reset => addrmap_r.RESET_ERROR.SOFTRESET.data(0) flag_reset => addrmap_r.RESET_ERROR.SOFTRESET.data(0)
); );
-- Pack fo convenience
m_axis_decoded_tdata <= m_axis_decoded_tdata_posx & m_axis_decoded_tdata_posy &
m_axis_decoded_tdata_bpmid & m_axis_decoded_tdata_faseq;
--------------- ---------------
-- GT WIZARD -- -- GT WIZARD --
--------------- ---------------
...@@ -349,7 +368,8 @@ begin ...@@ -349,7 +368,8 @@ begin
------------------- -------------------
inst_filter:entity work.combpm_packet_filter inst_filter:entity work.combpm_packet_filter
generic map( generic map(
G_W_ADDR_TABLE => C_W_ADDR_TABLE G_W_ADDR_TABLE => C_W_ADDR_TABLE,
G_W_TDATA => m_axis_decoded_tdata'length
) )
port map( port map(
axis_clk => usrclk, axis_clk => usrclk,
...@@ -357,13 +377,13 @@ begin ...@@ -357,13 +377,13 @@ begin
axis_rst_n => sync_resetn, axis_rst_n => sync_resetn,
-- AXIS SLAVE INTERFACE -- AXIS SLAVE INTERFACE
s_axis_tdest => m_axis_decoded_m2s.tdest, s_axis_tdata => m_axis_decoded_tdata,
s_axis_tdata => m_axis_decoded_m2s.tdata, s_axis_tuser_bpmid => m_axis_decoded_tdata_bpmid,
s_axis_tvalid => m_axis_decoded_m2s.tvalid, s_axis_tvalid => m_axis_decoded_tvalid,
-- AXIS SLAVE INTERFACE -- AXIS SLAVE INTERFACE
m_axis_tdest => m_axis_tdest, m_axis_tdest => m_axis_tdest,
m_axis_tdata => m_axis_tdata, m_axis_tdata => m_axis_filt_tdata,
m_axis_tvalid => m_axis_tvalid, m_axis_tvalid => m_axis_tvalid,
-- Table configuration interface -- Table configuration interface
...@@ -375,4 +395,10 @@ begin ...@@ -375,4 +395,10 @@ begin
); );
addrmap_w.filtertable.data(31 downto 8) <= (others => '0'); addrmap_w.filtertable.data(31 downto 8) <= (others => '0');
-- unpack
m_axis_tdata_posx <= m_axis_filt_tdata(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto C_W_POS+C_W_BPMID+C_W_SEQ);
m_axis_tdata_posy <= m_axis_filt_tdata(C_W_POS+C_W_BPMID+C_W_SEQ-1 downto C_W_BPMID+C_W_SEQ);
m_axis_tdata_bpmid <= m_axis_filt_tdata(C_W_BPMID+C_W_SEQ-1 downto C_W_SEQ);
m_axis_tdata_seq <= m_axis_filt_tdata(C_W_SEQ-1 downto 0);
end architecture struct; end architecture struct;
...@@ -104,4 +104,10 @@ addrmap combpm { ...@@ -104,4 +104,10 @@ addrmap combpm {
mementries = 2**`C_W_ADDR_TABLE; mementries = 2**`C_W_ADDR_TABLE;
} FILTERTABLE; } FILTERTABLE;
reg {
desc="Sequence numbering offset";
desyrdl_data_type="int16";
field {sw = rw; hw = r;} data[16]=0;
} SEQ_OFFSET;
}; };
...@@ -20,12 +20,11 @@ proc setSources {} { ...@@ -20,12 +20,11 @@ proc setSources {} {
# Generate VHDL package with modversion # Generate VHDL package with modversion
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm_version.vhd lappend Vhdl {"../hdl/pkg_combpm_version.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/pkg_combpm.vhd lappend Vhdl {"../hdl/pkg_combpm.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/combpm_protocol_electron.vhd lappend Vhdl {"../hdl/combpm_protocol_electron.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/top_combpm_electron.vhd lappend Vhdl {"../hdl/top_combpm_electron.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/pkg_bpmpacket_stream.vhd lappend Vhdl {"../hdl/combpm_packet_filter.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/combpm_packet_filter.vhd
} }
......