- Feb 04, 2022
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BRONES Romain authored
VHDL * Add attributes on interface ports. * Bring back QPLL andCDR lock signals on the GT wrapper TCL * Add simple address map
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- Feb 01, 2022
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BRONES Romain authored
* Corrections for synthesis * QPLL lock output signal TEMPORARY set to one !!
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- Jan 31, 2022
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BRONES Romain authored
* Use a package
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