fix: Add rising edge filter on PPS

* Sometimes 0 were read on the AXI interface. Hopefully this fixes this.

hdl/combpm_protocol_electron.vhd

@@ -84,6 +84,8 @@ architecture rtl of combpm_protocol_electron is
     signal packet            : t_bpmpacket;
     signal m_axi_tvalid      : std_logic;
 
+    signal pps_r             : std_logic;
+
 
 begin
 
@@ -287,8 +289,12 @@ begin
             last_cnt_seq_r      <= (others => '0');
             seq_discontinuity   <= '0';
             cnt_seq_mismatch    <= '0';
+            pps_r               <= '0';
         elsif rising_edge(clk) then
 
+            -- Register for rising edge filter
+            pps_r       <= pps;
+
             if soft_reset = '1' then
                 cnt_frame_seq_r <= (others => '0');
                 cnt_valid_r     <= (others => '0');
@@ -313,7 +319,7 @@ begin
                 end if;
 
                 -- Rate counter
-                if pps = '1' then
+                if pps = '1'  and pps_r = '0' then
                     frame_valid_rate     <= std_logic_vector(rate_valid_r);
                     frame_invalid_rate   <= std_logic_vector(rate_invalid_r);
                     rate_valid_r    <= (others => '0');