Correction for synthesis

Also add Makefile rule to perform synthesis of IP bloc

Makefile

@@ -28,9 +28,16 @@ hdl/combpm_protocol_electron_ctrl.vhd: rdl/combpm_protocol_electron_ctrl.rdl
 # Package IP
 ip:component.xml
 
-component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc) $(xcisrc)
+component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc)
 	vivado -mode batch -source tcl/combpm.tcl
 
+###############################################################################
+# Synthessize IP for test
+synth:component.xml
+	vivado -mode batch -source tcl/bloc_synthesis.tcl
+
+
+
 
 ###############################################################################
 # Cleaner Rules
@@ -48,4 +55,4 @@ clean-all:clean-ip clean
 	rm -f tcl/sources.tcl
 	rm -f hdl/combpm_protocol_electron_ctrl.vhd
 
-.PHONY: clean clean-ip clean-sim clean-all none ip sim
+.PHONY: clean clean-ip clean-sim clean-all none ip sim synth

hdl/top_combpm_electron.vhd

@@ -86,10 +86,68 @@ architecture struct of top_combpm_electron is
     ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
     ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
 
+    COMPONENT combpm_gtwizard
+      PORT (
+        gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+        gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+        gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+        txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+        txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+        txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+        gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+        rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+        rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+        rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+        rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+        rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+        rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+        txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+      );
+    END COMPONENT;
 
     ------------------------
     -- SIGNAL DECLARATION --
     ------------------------
+    signal usrclk        : std_logic;
     signal rst           : std_logic;
     signal tx_disable    : std_logic;
     signal rx_commadeten : std_logic;
@@ -144,12 +202,12 @@ begin
         gt_rxbyterealign_i    => gt_rxbyterealign,
         gt_rxcommadet_i       => gt_rxcommadet,
         gt_rxcommadeten_o     => rx_commadeten,
-        gt_rxresetdatapath_o  => gt_rxresetdatapath,
+        gt_rxrstdatapath_o    => gt_rxresetdatapath,
         protocol_framecnt_i   => frame_counter,
         protocol_frameerror_i => frame_error,
 
-        clk                   => clk,
-        reset                 => sync_rst,
+        clk                   => usrclk,
+        reset                 => rst,
         S_AXI_AWADDR          => S_AXI_AWADDR,
         S_AXI_AWPROT          => S_AXI_AWPROT,
         S_AXI_AWVALID         => S_AXI_AWVALID,
@@ -177,7 +235,7 @@ begin
     protocol_inst: entity work.combpm_protocol_electron
     port map(
         rst_n              => rst_n,
-        clk                => clk,
+        clk                => usrclk,
         gt_datarx          => gt_datarx,
         gt_datatx          => gt_datatx,
         gt_powergood       => gt_powergood,
@@ -229,7 +287,7 @@ begin
         gtwiz_reset_clk_freerun_in(0)         => free_100_clk,
 
         -- Clock and data
-        gtwiz_userclk_rx_usrclk_out(0)        => clk,
+        gtwiz_userclk_rx_usrclk_out(0)        => usrclk,
         gtwiz_userdata_tx_in                  => gt_datatx,
         gtwiz_userdata_rx_out                 => gt_datarx,
 
@@ -241,7 +299,7 @@ begin
 
         -- Control
         gtwiz_reset_rx_datapath_in(0)         => gt_rxresetdatapath,
-        rxbufreset_in(0)                      => "0",
+        rxbufreset_in                         => "0",
         rxcommadeten_in(0)                    => gt_rxcommadeten,
         rx8b10ben_in                          => "1",
         rxmcommaalignen_in                    => "1",
@@ -269,8 +327,8 @@ begin
         -- SFP
         gthrxn_in(0)                          => sfp_rxn,
         gthrxp_in(0)                          => sfp_rxp,
-        gthtxn_out                            => sfp_txn,
-        gthtxp_out                            => sfp_txp,
+        gthtxn_out(0)                         => sfp_txn,
+        gthtxp_out(0)                         => sfp_txp,
 
         -- Not used
         qpll0clk_in                           => "0",     -- not used
@@ -278,10 +336,10 @@ begin
         gtwiz_reset_rx_cdr_stable_out         => open, -- Do not use
         gtwiz_userclk_rx_srcclk_out           => open,
         gtwiz_userclk_rx_usrclk2_out          => open,
-        rxctrl0_out                           => (others => '0'),
-        rxctrl1_out                           => (others => '0'),
-        rxctrl2_out                           => (others => '0'),
-        rxctrl3_out                           => (others => '0'),
+        rxctrl0_out                           => open,
+        rxctrl1_out                           => open,
+        rxctrl2_out                           => open,
+        rxctrl3_out                           => open,
         txctrl0_in                            => (others => '0'),
         txctrl1_in                            => (others => '0'),
         txctrl2_in                            => (others => '0'),
@@ -290,6 +348,8 @@ begin
         gtwiz_userclk_tx_usrclk2_out          => open
     );
 
+    clk <= usrclk;
+
     -- SFP direct connexion
     gt_txfault      <= sfp_tx_fault;
     gt_rxlos        <= sfp_rx_los;

others/gthe_common.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity gthe_common is
+    port(
+        -- Differential clock intput
+        gtrefclk_p      : in std_logic;
+        gtrefclk_n      : in std_logic;
+
+        -- QPLL0 interface
+        qpll0reset      : in std_logic;
+        qpll0lock       : out std_logic;
+        qpll0outclk     : out std_logic;
+        qpll0refclk     : out std_logic;
+
+        -- QPLL0 interface
+        qpll1reset      : in std_logic;
+        qpll1lock       : out std_logic;
+        qpll1outclk     : out std_logic;
+        qpll1refclk     : out std_logic
+
+    );
+end entity gthe_common;
+
+architecture struct of gthe_common is
+
+    ATTRIBUTE X_INTERFACE_INFO : STRING;
+    ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
+    ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
+
+    signal gtrefclk : std_logic;
+
+    component combpm_gtwizard_gthe4_common_wrapper
+    port(
+        GTHE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
+        GTHE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
+        GTHE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
+        GTHE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTSOUTHREFCLK01 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTSOUTHREFCLK10 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_GTSOUTHREFCLK11 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_PCIERATEQPLL0 : in std_logic_vector(2 downto 0);
+        GTHE4_COMMON_PCIERATEQPLL1 : in std_logic_vector(2 downto 0);
+        GTHE4_COMMON_PMARSVD0 : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_PMARSVD1 : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLL0CLKRSVD0 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0CLKRSVD1 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0FBDIV : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLL0LOCKDETCLK : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0LOCKEN : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0PD : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0REFCLKSEL : in std_logic_vector(2 downto 0);
+        GTHE4_COMMON_QPLL0RESET : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1CLKRSVD0 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1CLKRSVD1 : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1FBDIV : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLL1LOCKDETCLK : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1LOCKEN : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1PD : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1REFCLKSEL : in std_logic_vector(2 downto 0);
+        GTHE4_COMMON_QPLL1RESET : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLLRSVD1 : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLLRSVD2 : in std_logic_vector(4 downto 0);
+        GTHE4_COMMON_QPLLRSVD3 : in std_logic_vector(4 downto 0);
+        GTHE4_COMMON_QPLLRSVD4 : in std_logic_vector(7 downto 0);
+        GTHE4_COMMON_RCALENB : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_SDM0DATA : in std_logic_vector(24 downto 0);
+        GTHE4_COMMON_SDM0RESET : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_SDM0TOGGLE : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_SDM0WIDTH : in std_logic_vector(1 downto 0);
+        GTHE4_COMMON_SDM1DATA : in std_logic_vector(24 downto 0);
+        GTHE4_COMMON_SDM1RESET : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_SDM1TOGGLE : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_SDM1WIDTH : in std_logic_vector(1 downto 0);
+        GTHE4_COMMON_TCONGPI : in std_logic_vector(9 downto 0);
+        GTHE4_COMMON_TCONPOWERUP : in std_logic_vector(0 downto 0);
+        GTHE4_COMMON_TCONRESET : in std_logic_vector(1 downto 0);
+        GTHE4_COMMON_TCONRSVDIN1 : in std_logic_vector(1 downto 0);
+        GTHE4_COMMON_DRPDO : out std_logic_vector(15 downto 0);
+        GTHE4_COMMON_DRPRDY : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_PMARSVDOUT0 : out std_logic_vector(7 downto 0);
+        GTHE4_COMMON_PMARSVDOUT1 : out std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLL0FBCLKLOST : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0LOCK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0OUTCLK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0OUTREFCLK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL0REFCLKLOST : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1FBCLKLOST : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1LOCK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1OUTCLK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1OUTREFCLK : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLL1REFCLKLOST : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_QPLLDMONITOR0 : out std_logic_vector(7 downto 0);
+        GTHE4_COMMON_QPLLDMONITOR1 : out std_logic_vector(7 downto 0);
+        GTHE4_COMMON_REFCLKOUTMONITOR0 : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_REFCLKOUTMONITOR1 : out std_logic_vector(0 downto 0);
+        GTHE4_COMMON_RXRECCLK0SEL : out std_logic_vector(1 downto 0);
+        GTHE4_COMMON_RXRECCLK1SEL : out std_logic_vector(1 downto 0);
+        GTHE4_COMMON_SDM0FINALOUT : out std_logic_vector(3 downto 0);
+        GTHE4_COMMON_SDM0TESTDATA : out std_logic_vector(14 downto 0);
+        GTHE4_COMMON_SDM1FINALOUT : out std_logic_vector(3 downto 0);
+        GTHE4_COMMON_SDM1TESTDATA : out std_logic_vector(14 downto 0);
+        GTHE4_COMMON_TCONGPO : out std_logic_vector(9 downto 0);
+        GTHE4_COMMON_TCONRSVDOUT0 : out std_logic_vector(0 downto 0)
+    );
+    end component;
+
+begin
+
+    -- INPUT BUFFER
+   IBUFDS_GTE4_inst : IBUFDS_GTE4
+   generic map (
+      REFCLK_EN_TX_PATH => '0',
+      REFCLK_HROW_CK_SEL => "00",
+      REFCLK_ICNTL_RX => "00"
+   )
+   port map (
+      O => gtrefclk,
+      ODIV2 => open,
+      CEB => '0',
+      I => gtrefclk_p,
+      IB => gtrefclk_n
+   );
+
+
+    -- TRANSCEIVER COMMON BLOCK
+    gthe4_common_wrapper_inst: combpm_gtwizard_gthe4_common_wrapper
+    port map(
+        GTHE4_COMMON_BGBYPASSB =>         "1",
+        GTHE4_COMMON_BGMONITORENB =>      "1",
+        GTHE4_COMMON_BGPDB =>             "1",
+        GTHE4_COMMON_BGRCALOVRD =>        "11111",
+        GTHE4_COMMON_BGRCALOVRDENB =>     "1",
+        GTHE4_COMMON_DRPADDR =>           "0000000000000000",
+        GTHE4_COMMON_DRPCLK =>            "0",
+        GTHE4_COMMON_DRPDI =>             "0000000000000000",
+        GTHE4_COMMON_DRPEN =>             "0",
+        GTHE4_COMMON_DRPWE =>             "0",
+        GTHE4_COMMON_GTGREFCLK0 =>        "0",
+        GTHE4_COMMON_GTGREFCLK1 =>        "0",
+        GTHE4_COMMON_GTNORTHREFCLK00 =>   "0",
+        GTHE4_COMMON_GTNORTHREFCLK01 =>   "0",
+        GTHE4_COMMON_GTNORTHREFCLK10 =>   "0",
+        GTHE4_COMMON_GTNORTHREFCLK11 =>   "0",
+        GTHE4_COMMON_GTREFCLK00(0) =>        gtrefclk,
+        GTHE4_COMMON_GTREFCLK01(0) =>        gtrefclk,
+        GTHE4_COMMON_GTREFCLK10 =>        "0",
+        GTHE4_COMMON_GTREFCLK11 =>        "0",
+        GTHE4_COMMON_GTSOUTHREFCLK00 =>   "0",
+        GTHE4_COMMON_GTSOUTHREFCLK01 =>   "0",
+        GTHE4_COMMON_GTSOUTHREFCLK10 =>   "0",
+        GTHE4_COMMON_GTSOUTHREFCLK11 =>   "0",
+        GTHE4_COMMON_PCIERATEQPLL0 =>     "000",
+        GTHE4_COMMON_PCIERATEQPLL1 =>     "000",
+        GTHE4_COMMON_PMARSVD0 =>          "00000000",
+        GTHE4_COMMON_PMARSVD1 =>          "00000000",
+        GTHE4_COMMON_QPLL0CLKRSVD0 =>     "0",
+        GTHE4_COMMON_QPLL0CLKRSVD1 =>     "0",
+        GTHE4_COMMON_QPLL0FBDIV =>        "00000000",
+        GTHE4_COMMON_QPLL0LOCKDETCLK =>   "0",
+        GTHE4_COMMON_QPLL0LOCKEN =>       "1",
+        GTHE4_COMMON_QPLL0PD =>           "0",
+        GTHE4_COMMON_QPLL0REFCLKSEL =>    "001",
+        GTHE4_COMMON_QPLL0RESET(0) =>        qpll0reset,
+        GTHE4_COMMON_QPLL1CLKRSVD0 =>     "0",
+        GTHE4_COMMON_QPLL1CLKRSVD1 =>     "0",
+        GTHE4_COMMON_QPLL1FBDIV =>        "00000000",
+        GTHE4_COMMON_QPLL1LOCKDETCLK =>   "0",
+        GTHE4_COMMON_QPLL1LOCKEN =>       "1",
+        GTHE4_COMMON_QPLL1PD =>           "0",
+        GTHE4_COMMON_QPLL1REFCLKSEL =>    "001",
+        GTHE4_COMMON_QPLL1RESET(0) =>        qpll1reset,
+        GTHE4_COMMON_QPLLRSVD1 =>         "00000000",
+        GTHE4_COMMON_QPLLRSVD2 =>         "00000",
+        GTHE4_COMMON_QPLLRSVD3 =>         "00000",
+        GTHE4_COMMON_QPLLRSVD4 =>         "00000000",
+        GTHE4_COMMON_RCALENB =>           "1",
+        GTHE4_COMMON_SDM0DATA =>          "0000000000000000000000000",
+        GTHE4_COMMON_SDM0RESET =>         "0",
+        GTHE4_COMMON_SDM0TOGGLE =>        "0",
+        GTHE4_COMMON_SDM0WIDTH =>         "00",
+        GTHE4_COMMON_SDM1DATA =>          "0010001011010000111001010",
+        GTHE4_COMMON_SDM1RESET =>         "0",
+        GTHE4_COMMON_SDM1TOGGLE =>        "0",
+        GTHE4_COMMON_SDM1WIDTH =>         "00",
+        GTHE4_COMMON_TCONGPI =>           "0000000000",
+        GTHE4_COMMON_TCONPOWERUP =>       "0",
+        GTHE4_COMMON_TCONRESET =>         "00",
+        GTHE4_COMMON_TCONRSVDIN1 =>       "00",
+        GTHE4_COMMON_DRPDO =>             open,
+        GTHE4_COMMON_DRPRDY =>            open,
+        GTHE4_COMMON_PMARSVDOUT0 =>       open,
+        GTHE4_COMMON_PMARSVDOUT1 =>       open,
+        GTHE4_COMMON_QPLL0FBCLKLOST =>    open,
+        GTHE4_COMMON_QPLL0LOCK(0) =>         qpll0lock,
+        GTHE4_COMMON_QPLL0OUTCLK(0) =>       qpll0outclk,
+        GTHE4_COMMON_QPLL0OUTREFCLK(0) =>    qpll0refclk,
+        GTHE4_COMMON_QPLL0REFCLKLOST =>   open,
+        GTHE4_COMMON_QPLL1FBCLKLOST =>    open,
+        GTHE4_COMMON_QPLL1LOCK(0) =>         qpll1lock,
+        GTHE4_COMMON_QPLL1OUTCLK(0) =>       qpll1outclk,
+        GTHE4_COMMON_QPLL1OUTREFCLK(0) =>    qpll1refclk,
+        GTHE4_COMMON_QPLL1REFCLKLOST =>   open,
+        GTHE4_COMMON_QPLLDMONITOR0 =>     open,
+        GTHE4_COMMON_QPLLDMONITOR1 =>     open,
+        GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
+        GTHE4_COMMON_REFCLKOUTMONITOR1 => open,
+        GTHE4_COMMON_RXRECCLK0SEL =>      open,
+        GTHE4_COMMON_RXRECCLK1SEL =>      open,
+        GTHE4_COMMON_SDM0FINALOUT =>      open,
+        GTHE4_COMMON_SDM0TESTDATA =>      open,
+        GTHE4_COMMON_SDM1FINALOUT =>      open,
+        GTHE4_COMMON_SDM1TESTDATA =>      open,
+        GTHE4_COMMON_TCONGPO =>           open,
+        GTHE4_COMMON_TCONRSVDOUT0 =>      open
+    );
+
+end architecture struct;

tcl/bloc_synthesis.tcl

+# Source metadata
+source ./tcl/metadata.tcl
+
+# Create project
+create_project synth_project -part ${part} -in_memory
+set_property source_mgmt_mode All [current_project]
+
+set_property IP_REPO_PATHS . [current_fileset]
+update_ip_catalog
+
+# Create instance of the IP
+create_ip -vendor ${vlnv_vendor} -library "user" -name "combpm" -module_name combpm_0
+
+# Generate output products
+#generate_target all [get_ips combpm_0]
+
+# Try synthesis
+synth_ip [get_ips combpm_0]
+
+close_project