diff --git a/Makefile b/Makefile
index 7d8f13854555491ebdf01badcfa5c28582d74641..29cc228839e0564ee3153af30764cfbf8d796dc4 100644
--- a/Makefile
+++ b/Makefile
@@ -28,9 +28,16 @@ hdl/combpm_protocol_electron_ctrl.vhd: rdl/combpm_protocol_electron_ctrl.rdl
# Package IP
ip:component.xml
-component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc) $(xcisrc)
+component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc)
vivado -mode batch -source tcl/combpm.tcl
+###############################################################################
+# Synthessize IP for test
+synth:component.xml
+ vivado -mode batch -source tcl/bloc_synthesis.tcl
+
+
+
###############################################################################
# Cleaner Rules
@@ -48,4 +55,4 @@ clean-all:clean-ip clean
rm -f tcl/sources.tcl
rm -f hdl/combpm_protocol_electron_ctrl.vhd
-.PHONY: clean clean-ip clean-sim clean-all none ip sim
+.PHONY: clean clean-ip clean-sim clean-all none ip sim synth
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 415a22a080060a9279136b076e3ae924093785ce..b7968ec864a324bde06282cd427b4cc5e98c0ad8 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -86,10 +86,68 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
+ COMPONENT combpm_gtwizard
+ PORT (
+ gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+ END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
+ signal usrclk : std_logic;
signal rst : std_logic;
signal tx_disable : std_logic;
signal rx_commadeten : std_logic;
@@ -144,12 +202,12 @@ begin
gt_rxbyterealign_i => gt_rxbyterealign,
gt_rxcommadet_i => gt_rxcommadet,
gt_rxcommadeten_o => rx_commadeten,
- gt_rxresetdatapath_o => gt_rxresetdatapath,
+ gt_rxrstdatapath_o => gt_rxresetdatapath,
protocol_framecnt_i => frame_counter,
protocol_frameerror_i => frame_error,
- clk => clk,
- reset => sync_rst,
+ clk => usrclk,
+ reset => rst,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
S_AXI_AWVALID => S_AXI_AWVALID,
@@ -177,7 +235,7 @@ begin
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => rst_n,
- clk => clk,
+ clk => usrclk,
gt_datarx => gt_datarx,
gt_datatx => gt_datatx,
gt_powergood => gt_powergood,
@@ -229,7 +287,7 @@ begin
gtwiz_reset_clk_freerun_in(0) => free_100_clk,
-- Clock and data
- gtwiz_userclk_rx_usrclk_out(0) => clk,
+ gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userdata_tx_in => gt_datatx,
gtwiz_userdata_rx_out => gt_datarx,
@@ -241,7 +299,7 @@ begin
-- Control
gtwiz_reset_rx_datapath_in(0) => gt_rxresetdatapath,
- rxbufreset_in(0) => "0",
+ rxbufreset_in => "0",
rxcommadeten_in(0) => gt_rxcommadeten,
rx8b10ben_in => "1",
rxmcommaalignen_in => "1",
@@ -269,8 +327,8 @@ begin
-- SFP
gthrxn_in(0) => sfp_rxn,
gthrxp_in(0) => sfp_rxp,
- gthtxn_out => sfp_txn,
- gthtxp_out => sfp_txp,
+ gthtxn_out(0) => sfp_txn,
+ gthtxp_out(0) => sfp_txp,
-- Not used
qpll0clk_in => "0", -- not used
@@ -278,10 +336,10 @@ begin
gtwiz_reset_rx_cdr_stable_out => open, -- Do not use
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk2_out => open,
- rxctrl0_out => (others => '0'),
- rxctrl1_out => (others => '0'),
- rxctrl2_out => (others => '0'),
- rxctrl3_out => (others => '0'),
+ rxctrl0_out => open,
+ rxctrl1_out => open,
+ rxctrl2_out => open,
+ rxctrl3_out => open,
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
@@ -290,6 +348,8 @@ begin
gtwiz_userclk_tx_usrclk2_out => open
);
+ clk <= usrclk;
+
-- SFP direct connexion
gt_txfault <= sfp_tx_fault;
gt_rxlos <= sfp_rx_los;
diff --git a/others/combpm_gtwizard_gthe4_common_wrapper.v b/others/combpm_gtwizard_gthe4_common_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..5085df4597ec33d6d573566bf1fe2e52ccef9cd3
--- /dev/null
+++ b/others/combpm_gtwizard_gthe4_common_wrapper.v
@@ -0,0 +1,397 @@
+
+
+`timescale 1ps/1ps
+module combpm_gtwizard_gthe4_common_wrapper (
+ input [0:0] GTHE4_COMMON_BGBYPASSB,
+ input [0:0] GTHE4_COMMON_BGMONITORENB,
+ input [0:0] GTHE4_COMMON_BGPDB,
+ input [4:0] GTHE4_COMMON_BGRCALOVRD,
+ input [0:0] GTHE4_COMMON_BGRCALOVRDENB,
+ input [15:0] GTHE4_COMMON_DRPADDR,
+ input [0:0] GTHE4_COMMON_DRPCLK,
+ input [15:0] GTHE4_COMMON_DRPDI,
+ input [0:0] GTHE4_COMMON_DRPEN,
+ input [0:0] GTHE4_COMMON_DRPWE,
+ input [0:0] GTHE4_COMMON_GTGREFCLK0,
+ input [0:0] GTHE4_COMMON_GTGREFCLK1,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK00,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK01,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK10,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK11,
+ input [0:0] GTHE4_COMMON_GTREFCLK00,
+ input [0:0] GTHE4_COMMON_GTREFCLK01,
+ input [0:0] GTHE4_COMMON_GTREFCLK10,
+ input [0:0] GTHE4_COMMON_GTREFCLK11,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK00,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK01,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK10,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK11,
+ input [2:0] GTHE4_COMMON_PCIERATEQPLL0,
+ input [2:0] GTHE4_COMMON_PCIERATEQPLL1,
+ input [7:0] GTHE4_COMMON_PMARSVD0,
+ input [7:0] GTHE4_COMMON_PMARSVD1,
+ input [0:0] GTHE4_COMMON_QPLL0CLKRSVD0,
+ input [0:0] GTHE4_COMMON_QPLL0CLKRSVD1,
+ input [7:0] GTHE4_COMMON_QPLL0FBDIV,
+ input [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK,
+ input [0:0] GTHE4_COMMON_QPLL0LOCKEN,
+ input [0:0] GTHE4_COMMON_QPLL0PD,
+ input [2:0] GTHE4_COMMON_QPLL0REFCLKSEL,
+ input [0:0] GTHE4_COMMON_QPLL0RESET,
+ input [0:0] GTHE4_COMMON_QPLL1CLKRSVD0,
+ input [0:0] GTHE4_COMMON_QPLL1CLKRSVD1,
+ input [7:0] GTHE4_COMMON_QPLL1FBDIV,
+ input [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK,
+ input [0:0] GTHE4_COMMON_QPLL1LOCKEN,
+ input [0:0] GTHE4_COMMON_QPLL1PD,
+ input [2:0] GTHE4_COMMON_QPLL1REFCLKSEL,
+ input [0:0] GTHE4_COMMON_QPLL1RESET,
+ input [7:0] GTHE4_COMMON_QPLLRSVD1,
+ input [4:0] GTHE4_COMMON_QPLLRSVD2,
+ input [4:0] GTHE4_COMMON_QPLLRSVD3,
+ input [7:0] GTHE4_COMMON_QPLLRSVD4,
+ input [0:0] GTHE4_COMMON_RCALENB,
+ input [24:0] GTHE4_COMMON_SDM0DATA,
+ input [0:0] GTHE4_COMMON_SDM0RESET,
+ input [0:0] GTHE4_COMMON_SDM0TOGGLE,
+ input [1:0] GTHE4_COMMON_SDM0WIDTH,
+ input [24:0] GTHE4_COMMON_SDM1DATA,
+ input [0:0] GTHE4_COMMON_SDM1RESET,
+ input [0:0] GTHE4_COMMON_SDM1TOGGLE,
+ input [1:0] GTHE4_COMMON_SDM1WIDTH,
+ input [9:0] GTHE4_COMMON_TCONGPI,
+ input [0:0] GTHE4_COMMON_TCONPOWERUP,
+ input [1:0] GTHE4_COMMON_TCONRESET,
+ input [1:0] GTHE4_COMMON_TCONRSVDIN1,
+
+ output [15:0] GTHE4_COMMON_DRPDO,
+ output [0:0] GTHE4_COMMON_DRPRDY,
+ output [7:0] GTHE4_COMMON_PMARSVDOUT0,
+ output [7:0] GTHE4_COMMON_PMARSVDOUT1,
+ output [0:0] GTHE4_COMMON_QPLL0FBCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL0LOCK,
+ output [0:0] GTHE4_COMMON_QPLL0OUTCLK,
+ output [0:0] GTHE4_COMMON_QPLL0OUTREFCLK,
+ output [0:0] GTHE4_COMMON_QPLL0REFCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL1FBCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL1LOCK,
+ output [0:0] GTHE4_COMMON_QPLL1OUTCLK,
+ output [0:0] GTHE4_COMMON_QPLL1OUTREFCLK,
+ output [0:0] GTHE4_COMMON_QPLL1REFCLKLOST,
+ output [7:0] GTHE4_COMMON_QPLLDMONITOR0,
+ output [7:0] GTHE4_COMMON_QPLLDMONITOR1,
+ output [0:0] GTHE4_COMMON_REFCLKOUTMONITOR0,
+ output [0:0] GTHE4_COMMON_REFCLKOUTMONITOR1,
+ output [1:0] GTHE4_COMMON_RXRECCLK0SEL,
+ output [1:0] GTHE4_COMMON_RXRECCLK1SEL,
+ output [3:0] GTHE4_COMMON_SDM0FINALOUT,
+ output [14:0] GTHE4_COMMON_SDM0TESTDATA,
+ output [3:0] GTHE4_COMMON_SDM1FINALOUT,
+ output [14:0] GTHE4_COMMON_SDM1TESTDATA,
+ output [9:0] GTHE4_COMMON_TCONGPO,
+ output [0:0] GTHE4_COMMON_TCONRSVDOUT0
+);
+
+
+
+gtwizard_ultrascale_v1_7_9_gthe4_common #(
+ .GTHE4_COMMON_AEN_QPLL0_FBDIV (1'b1),
+ .GTHE4_COMMON_AEN_QPLL1_FBDIV (1'b1),
+ .GTHE4_COMMON_AEN_SDM0TOGGLE (1'b0),
+ .GTHE4_COMMON_AEN_SDM1TOGGLE (1'b0),
+ .GTHE4_COMMON_A_SDM0TOGGLE (1'b0),
+ .GTHE4_COMMON_A_SDM1DATA_HIGH (9'b000000000),
+ .GTHE4_COMMON_A_SDM1DATA_LOW (16'b0000000000000000),
+ .GTHE4_COMMON_A_SDM1TOGGLE (1'b0),
+ .GTHE4_COMMON_BGBYPASSB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGBYPASSB_VAL (1'b1),
+ .GTHE4_COMMON_BGMONITORENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGMONITORENB_VAL (1'b1),
+ .GTHE4_COMMON_BGPDB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGPDB_VAL (1'b1),
+ .GTHE4_COMMON_BGRCALOVRDENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGRCALOVRDENB_VAL (1'b1),
+ .GTHE4_COMMON_BGRCALOVRD_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGRCALOVRD_VAL (5'b11111),
+ .GTHE4_COMMON_BIAS_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_BIAS_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_BIAS_CFG2 (16'b0000000100100100),
+ .GTHE4_COMMON_BIAS_CFG3 (16'b0000000001000001),
+ .GTHE4_COMMON_BIAS_CFG4 (16'b0000000000010000),
+ .GTHE4_COMMON_BIAS_CFG_RSVD (16'b0000000000000000),
+ .GTHE4_COMMON_COMMON_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_COMMON_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_DRPADDR_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPADDR_VAL (16'b0000000000000000),
+ .GTHE4_COMMON_DRPCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPCLK_VAL (1'b0),
+ .GTHE4_COMMON_DRPDI_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPDI_VAL (16'b0000000000000000),
+ .GTHE4_COMMON_DRPEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPEN_VAL (1'b0),
+ .GTHE4_COMMON_DRPWE_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPWE_VAL (1'b0),
+ .GTHE4_COMMON_GTGREFCLK0_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTGREFCLK0_VAL (1'b0),
+ .GTHE4_COMMON_GTGREFCLK1_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTGREFCLK1_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL0_TIE_EN (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL0_VAL (3'b000),
+ .GTHE4_COMMON_PCIERATEQPLL1_TIE_EN (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL1_VAL (3'b000),
+ .GTHE4_COMMON_PMARSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_PMARSVD0_VAL (8'b00000000),
+ .GTHE4_COMMON_PMARSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_PMARSVD1_VAL (8'b00000000),
+ .GTHE4_COMMON_POR_CFG (16'b0000000000000000),
+ .GTHE4_COMMON_PPF0_CFG (16'b0000011000000000),
+ .GTHE4_COMMON_PPF1_CFG (16'b0000011000000000),
+ .GTHE4_COMMON_QPLL0CLKOUT_RATE ("HALF"),
+ .GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD0_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0FBDIV_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0FBDIV_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKEN_VAL (1'b1),
+ .GTHE4_COMMON_QPLL0PD_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0PD_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0REFCLKSEL_VAL (3'b001),
+ .GTHE4_COMMON_QPLL0RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0RESET_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0_CFG0 (16'b0011001100011100),
+ .GTHE4_COMMON_QPLL0_CFG1 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL0_CFG1_G3 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL0_CFG2 (16'b0000111111000000),
+ .GTHE4_COMMON_QPLL0_CFG2_G3 (16'b0000111111000000),
+ .GTHE4_COMMON_QPLL0_CFG3 (16'b0000000100100000),
+ .GTHE4_COMMON_QPLL0_CFG4 (16'b0000000000000011),
+ .GTHE4_COMMON_QPLL0_CP (10'b0011111111),
+ .GTHE4_COMMON_QPLL0_CP_G3 (10'b0000001111),
+ .GTHE4_COMMON_QPLL0_FBDIV (66),
+ .GTHE4_COMMON_QPLL0_FBDIV_G3 (160),
+ .GTHE4_COMMON_QPLL0_INIT_CFG0 (16'b0000001010110010),
+ .GTHE4_COMMON_QPLL0_INIT_CFG1 (8'b00000000),
+ .GTHE4_COMMON_QPLL0_LOCK_CFG (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL0_LPF (10'b1000111111),
+ .GTHE4_COMMON_QPLL0_LPF_G3 (10'b0111010101),
+ .GTHE4_COMMON_QPLL0_PCI_EN (1'b0),
+ .GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP (1'b1),
+ .GTHE4_COMMON_QPLL0_REFCLK_DIV (1),
+ .GTHE4_COMMON_QPLL0_SDM_CFG0 (16'b0000000010000000),
+ .GTHE4_COMMON_QPLL0_SDM_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL0_SDM_CFG2 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1CLKOUT_RATE ("HALF"),
+ .GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD0_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1FBDIV_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1FBDIV_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKEN_VAL (1'b1),
+ .GTHE4_COMMON_QPLL1PD_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1PD_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1REFCLKSEL_VAL (3'b001),
+ .GTHE4_COMMON_QPLL1RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1RESET_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1_CFG0 (16'b0011001100011100),
+ .GTHE4_COMMON_QPLL1_CFG1 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL1_CFG1_G3 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL1_CFG2 (16'b0000111111000011),
+ .GTHE4_COMMON_QPLL1_CFG2_G3 (16'b0000111111000011),
+ .GTHE4_COMMON_QPLL1_CFG3 (16'b0000000100100000),
+ .GTHE4_COMMON_QPLL1_CFG4 (16'b0000000000000011),
+ .GTHE4_COMMON_QPLL1_CP (10'b0011111111),
+ .GTHE4_COMMON_QPLL1_CP_G3 (10'b0001111111),
+ .GTHE4_COMMON_QPLL1_FBDIV (54),
+ .GTHE4_COMMON_QPLL1_FBDIV_G3 (80),
+ .GTHE4_COMMON_QPLL1_INIT_CFG0 (16'b0000001010110010),
+ .GTHE4_COMMON_QPLL1_INIT_CFG1 (8'b00000000),
+ .GTHE4_COMMON_QPLL1_LOCK_CFG (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL1_LPF (10'b1000011111),
+ .GTHE4_COMMON_QPLL1_LPF_G3 (10'b0111010100),
+ .GTHE4_COMMON_QPLL1_PCI_EN (1'b0),
+ .GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP (1'b1),
+ .GTHE4_COMMON_QPLL1_REFCLK_DIV (1),
+ .GTHE4_COMMON_QPLL1_SDM_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1_SDM_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1_SDM_CFG2 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLLRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD1_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLLRSVD2_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD2_VAL (5'b00000),
+ .GTHE4_COMMON_QPLLRSVD3_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD3_VAL (5'b00000),
+ .GTHE4_COMMON_QPLLRSVD4_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD4_VAL (8'b00000000),
+ .GTHE4_COMMON_RCALENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_RCALENB_VAL (1'b1),
+ .GTHE4_COMMON_RSVD_ATTR0 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR1 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR2 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR3 (16'b0000000000000000),
+ .GTHE4_COMMON_RXRECCLKOUT0_SEL (2'b00),
+ .GTHE4_COMMON_RXRECCLKOUT1_SEL (2'b00),
+ .GTHE4_COMMON_SARC_ENB (1'b0),
+ .GTHE4_COMMON_SARC_SEL (1'b0),
+ .GTHE4_COMMON_SDM0DATA_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0DATA_VAL (25'b0000000000000000000000000),
+ .GTHE4_COMMON_SDM0INITSEED0_0 (16'b0000000100010001),
+ .GTHE4_COMMON_SDM0INITSEED0_1 (9'b000010001),
+ .GTHE4_COMMON_SDM0RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0RESET_VAL (1'b0),
+ .GTHE4_COMMON_SDM0TOGGLE_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0TOGGLE_VAL (1'b0),
+ .GTHE4_COMMON_SDM0WIDTH_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0WIDTH_VAL (2'b00),
+ .GTHE4_COMMON_SDM1DATA_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1DATA_VAL (25'b0010001011010000111001010),
+ .GTHE4_COMMON_SDM1INITSEED0_0 (16'b0000000100010001),
+ .GTHE4_COMMON_SDM1INITSEED0_1 (9'b000010001),
+ .GTHE4_COMMON_SDM1RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1RESET_VAL (1'b0),
+ .GTHE4_COMMON_SDM1TOGGLE_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1TOGGLE_VAL (1'b0),
+ .GTHE4_COMMON_SDM1WIDTH_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1WIDTH_VAL (2'b00),
+ .GTHE4_COMMON_SIM_DEVICE ("ULTRASCALE_PLUS"),
+ .GTHE4_COMMON_SIM_MODE ("FAST"),
+ .GTHE4_COMMON_SIM_RESET_SPEEDUP ("TRUE"),
+ .GTHE4_COMMON_TCONGPI_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONGPI_VAL (10'b0000000000),
+ .GTHE4_COMMON_TCONPOWERUP_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONPOWERUP_VAL (1'b0),
+ .GTHE4_COMMON_TCONRESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONRESET_VAL (2'b00),
+ .GTHE4_COMMON_TCONRSVDIN1_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONRSVDIN1_VAL (2'b00)
+) common_inst (
+
+ // inputs
+ .GTHE4_COMMON_BGBYPASSB (GTHE4_COMMON_BGBYPASSB),
+ .GTHE4_COMMON_BGMONITORENB (GTHE4_COMMON_BGMONITORENB),
+ .GTHE4_COMMON_BGPDB (GTHE4_COMMON_BGPDB),
+ .GTHE4_COMMON_BGRCALOVRD (GTHE4_COMMON_BGRCALOVRD),
+ .GTHE4_COMMON_BGRCALOVRDENB (GTHE4_COMMON_BGRCALOVRDENB),
+ .GTHE4_COMMON_DRPADDR (GTHE4_COMMON_DRPADDR),
+ .GTHE4_COMMON_DRPCLK (GTHE4_COMMON_DRPCLK),
+ .GTHE4_COMMON_DRPDI (GTHE4_COMMON_DRPDI),
+ .GTHE4_COMMON_DRPEN (GTHE4_COMMON_DRPEN),
+ .GTHE4_COMMON_DRPWE (GTHE4_COMMON_DRPWE),
+ .GTHE4_COMMON_GTGREFCLK0 (GTHE4_COMMON_GTGREFCLK0),
+ .GTHE4_COMMON_GTGREFCLK1 (GTHE4_COMMON_GTGREFCLK1),
+ .GTHE4_COMMON_GTNORTHREFCLK00 (GTHE4_COMMON_GTNORTHREFCLK00),
+ .GTHE4_COMMON_GTNORTHREFCLK01 (GTHE4_COMMON_GTNORTHREFCLK01),
+ .GTHE4_COMMON_GTNORTHREFCLK10 (GTHE4_COMMON_GTNORTHREFCLK10),
+ .GTHE4_COMMON_GTNORTHREFCLK11 (GTHE4_COMMON_GTNORTHREFCLK11),
+ .GTHE4_COMMON_GTREFCLK00 (GTHE4_COMMON_GTREFCLK00),
+ .GTHE4_COMMON_GTREFCLK01 (GTHE4_COMMON_GTREFCLK01),
+ .GTHE4_COMMON_GTREFCLK10 (GTHE4_COMMON_GTREFCLK10),
+ .GTHE4_COMMON_GTREFCLK11 (GTHE4_COMMON_GTREFCLK11),
+ .GTHE4_COMMON_GTSOUTHREFCLK00 (GTHE4_COMMON_GTSOUTHREFCLK00),
+ .GTHE4_COMMON_GTSOUTHREFCLK01 (GTHE4_COMMON_GTSOUTHREFCLK01),
+ .GTHE4_COMMON_GTSOUTHREFCLK10 (GTHE4_COMMON_GTSOUTHREFCLK10),
+ .GTHE4_COMMON_GTSOUTHREFCLK11 (GTHE4_COMMON_GTSOUTHREFCLK11),
+ .GTHE4_COMMON_PCIERATEQPLL0 (GTHE4_COMMON_PCIERATEQPLL0),
+ .GTHE4_COMMON_PCIERATEQPLL1 (GTHE4_COMMON_PCIERATEQPLL1),
+ .GTHE4_COMMON_PMARSVD0 (GTHE4_COMMON_PMARSVD0),
+ .GTHE4_COMMON_PMARSVD1 (GTHE4_COMMON_PMARSVD1),
+ .GTHE4_COMMON_QPLL0CLKRSVD0 (GTHE4_COMMON_QPLL0CLKRSVD0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1 (GTHE4_COMMON_QPLL0CLKRSVD1),
+ .GTHE4_COMMON_QPLL0FBDIV (GTHE4_COMMON_QPLL0FBDIV),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK (GTHE4_COMMON_QPLL0LOCKDETCLK),
+ .GTHE4_COMMON_QPLL0LOCKEN (GTHE4_COMMON_QPLL0LOCKEN),
+ .GTHE4_COMMON_QPLL0PD (GTHE4_COMMON_QPLL0PD),
+ .GTHE4_COMMON_QPLL0REFCLKSEL (GTHE4_COMMON_QPLL0REFCLKSEL),
+ .GTHE4_COMMON_QPLL0RESET (GTHE4_COMMON_QPLL0RESET),
+ .GTHE4_COMMON_QPLL1CLKRSVD0 (GTHE4_COMMON_QPLL1CLKRSVD0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1 (GTHE4_COMMON_QPLL1CLKRSVD1),
+ .GTHE4_COMMON_QPLL1FBDIV (GTHE4_COMMON_QPLL1FBDIV),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK (GTHE4_COMMON_QPLL1LOCKDETCLK),
+ .GTHE4_COMMON_QPLL1LOCKEN (GTHE4_COMMON_QPLL1LOCKEN),
+ .GTHE4_COMMON_QPLL1PD (GTHE4_COMMON_QPLL1PD),
+ .GTHE4_COMMON_QPLL1REFCLKSEL (GTHE4_COMMON_QPLL1REFCLKSEL),
+ .GTHE4_COMMON_QPLL1RESET (GTHE4_COMMON_QPLL1RESET),
+ .GTHE4_COMMON_QPLLRSVD1 (GTHE4_COMMON_QPLLRSVD1),
+ .GTHE4_COMMON_QPLLRSVD2 (GTHE4_COMMON_QPLLRSVD2),
+ .GTHE4_COMMON_QPLLRSVD3 (GTHE4_COMMON_QPLLRSVD3),
+ .GTHE4_COMMON_QPLLRSVD4 (GTHE4_COMMON_QPLLRSVD4),
+ .GTHE4_COMMON_RCALENB (GTHE4_COMMON_RCALENB),
+ .GTHE4_COMMON_SDM0DATA (GTHE4_COMMON_SDM0DATA),
+ .GTHE4_COMMON_SDM0RESET (GTHE4_COMMON_SDM0RESET),
+ .GTHE4_COMMON_SDM0TOGGLE (GTHE4_COMMON_SDM0TOGGLE),
+ .GTHE4_COMMON_SDM0WIDTH (GTHE4_COMMON_SDM0WIDTH),
+ .GTHE4_COMMON_SDM1DATA (GTHE4_COMMON_SDM1DATA),
+ .GTHE4_COMMON_SDM1RESET (GTHE4_COMMON_SDM1RESET),
+ .GTHE4_COMMON_SDM1TOGGLE (GTHE4_COMMON_SDM1TOGGLE),
+ .GTHE4_COMMON_SDM1WIDTH (GTHE4_COMMON_SDM1WIDTH),
+ .GTHE4_COMMON_TCONGPI (GTHE4_COMMON_TCONGPI),
+ .GTHE4_COMMON_TCONPOWERUP (GTHE4_COMMON_TCONPOWERUP),
+ .GTHE4_COMMON_TCONRESET (GTHE4_COMMON_TCONRESET),
+ .GTHE4_COMMON_TCONRSVDIN1 (GTHE4_COMMON_TCONRSVDIN1),
+
+ // outputs
+ .GTHE4_COMMON_DRPDO (GTHE4_COMMON_DRPDO),
+ .GTHE4_COMMON_DRPRDY (GTHE4_COMMON_DRPRDY),
+ .GTHE4_COMMON_PMARSVDOUT0 (GTHE4_COMMON_PMARSVDOUT0),
+ .GTHE4_COMMON_PMARSVDOUT1 (GTHE4_COMMON_PMARSVDOUT1),
+ .GTHE4_COMMON_QPLL0FBCLKLOST (GTHE4_COMMON_QPLL0FBCLKLOST),
+ .GTHE4_COMMON_QPLL0LOCK (GTHE4_COMMON_QPLL0LOCK),
+ .GTHE4_COMMON_QPLL0OUTCLK (GTHE4_COMMON_QPLL0OUTCLK),
+ .GTHE4_COMMON_QPLL0OUTREFCLK (GTHE4_COMMON_QPLL0OUTREFCLK),
+ .GTHE4_COMMON_QPLL0REFCLKLOST (GTHE4_COMMON_QPLL0REFCLKLOST),
+ .GTHE4_COMMON_QPLL1FBCLKLOST (GTHE4_COMMON_QPLL1FBCLKLOST),
+ .GTHE4_COMMON_QPLL1LOCK (GTHE4_COMMON_QPLL1LOCK),
+ .GTHE4_COMMON_QPLL1OUTCLK (GTHE4_COMMON_QPLL1OUTCLK),
+ .GTHE4_COMMON_QPLL1OUTREFCLK (GTHE4_COMMON_QPLL1OUTREFCLK),
+ .GTHE4_COMMON_QPLL1REFCLKLOST (GTHE4_COMMON_QPLL1REFCLKLOST),
+ .GTHE4_COMMON_QPLLDMONITOR0 (GTHE4_COMMON_QPLLDMONITOR0),
+ .GTHE4_COMMON_QPLLDMONITOR1 (GTHE4_COMMON_QPLLDMONITOR1),
+ .GTHE4_COMMON_REFCLKOUTMONITOR0 (GTHE4_COMMON_REFCLKOUTMONITOR0),
+ .GTHE4_COMMON_REFCLKOUTMONITOR1 (GTHE4_COMMON_REFCLKOUTMONITOR1),
+ .GTHE4_COMMON_RXRECCLK0SEL (GTHE4_COMMON_RXRECCLK0SEL),
+ .GTHE4_COMMON_RXRECCLK1SEL (GTHE4_COMMON_RXRECCLK1SEL),
+ .GTHE4_COMMON_SDM0FINALOUT (GTHE4_COMMON_SDM0FINALOUT),
+ .GTHE4_COMMON_SDM0TESTDATA (GTHE4_COMMON_SDM0TESTDATA),
+ .GTHE4_COMMON_SDM1FINALOUT (GTHE4_COMMON_SDM1FINALOUT),
+ .GTHE4_COMMON_SDM1TESTDATA (GTHE4_COMMON_SDM1TESTDATA),
+ .GTHE4_COMMON_TCONGPO (GTHE4_COMMON_TCONGPO),
+ .GTHE4_COMMON_TCONRSVDOUT0 (GTHE4_COMMON_TCONRSVDOUT0)
+);
+
+endmodule
+
diff --git a/others/gthe_common.vhd b/others/gthe_common.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..fdbd8d3915018145a3d929977927fee9e6971971
--- /dev/null
+++ b/others/gthe_common.vhd
@@ -0,0 +1,238 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity gthe_common is
+ port(
+ -- Differential clock intput
+ gtrefclk_p : in std_logic;
+ gtrefclk_n : in std_logic;
+
+ -- QPLL0 interface
+ qpll0reset : in std_logic;
+ qpll0lock : out std_logic;
+ qpll0outclk : out std_logic;
+ qpll0refclk : out std_logic;
+
+ -- QPLL0 interface
+ qpll1reset : in std_logic;
+ qpll1lock : out std_logic;
+ qpll1outclk : out std_logic;
+ qpll1refclk : out std_logic
+
+ );
+end entity gthe_common;
+
+architecture struct of gthe_common is
+
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
+ ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
+
+ signal gtrefclk : std_logic;
+
+ component combpm_gtwizard_gthe4_common_wrapper
+ port(
+ GTHE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
+ GTHE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
+ GTHE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
+ GTHE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTSOUTHREFCLK01 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTSOUTHREFCLK10 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_GTSOUTHREFCLK11 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_PCIERATEQPLL0 : in std_logic_vector(2 downto 0);
+ GTHE4_COMMON_PCIERATEQPLL1 : in std_logic_vector(2 downto 0);
+ GTHE4_COMMON_PMARSVD0 : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_PMARSVD1 : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLL0CLKRSVD0 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0CLKRSVD1 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0FBDIV : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLL0LOCKDETCLK : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0LOCKEN : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0PD : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0REFCLKSEL : in std_logic_vector(2 downto 0);
+ GTHE4_COMMON_QPLL0RESET : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1CLKRSVD0 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1CLKRSVD1 : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1FBDIV : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLL1LOCKDETCLK : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1LOCKEN : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1PD : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1REFCLKSEL : in std_logic_vector(2 downto 0);
+ GTHE4_COMMON_QPLL1RESET : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLLRSVD1 : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLLRSVD2 : in std_logic_vector(4 downto 0);
+ GTHE4_COMMON_QPLLRSVD3 : in std_logic_vector(4 downto 0);
+ GTHE4_COMMON_QPLLRSVD4 : in std_logic_vector(7 downto 0);
+ GTHE4_COMMON_RCALENB : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_SDM0DATA : in std_logic_vector(24 downto 0);
+ GTHE4_COMMON_SDM0RESET : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_SDM0TOGGLE : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_SDM0WIDTH : in std_logic_vector(1 downto 0);
+ GTHE4_COMMON_SDM1DATA : in std_logic_vector(24 downto 0);
+ GTHE4_COMMON_SDM1RESET : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_SDM1TOGGLE : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_SDM1WIDTH : in std_logic_vector(1 downto 0);
+ GTHE4_COMMON_TCONGPI : in std_logic_vector(9 downto 0);
+ GTHE4_COMMON_TCONPOWERUP : in std_logic_vector(0 downto 0);
+ GTHE4_COMMON_TCONRESET : in std_logic_vector(1 downto 0);
+ GTHE4_COMMON_TCONRSVDIN1 : in std_logic_vector(1 downto 0);
+ GTHE4_COMMON_DRPDO : out std_logic_vector(15 downto 0);
+ GTHE4_COMMON_DRPRDY : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_PMARSVDOUT0 : out std_logic_vector(7 downto 0);
+ GTHE4_COMMON_PMARSVDOUT1 : out std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLL0FBCLKLOST : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0LOCK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0OUTCLK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0OUTREFCLK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL0REFCLKLOST : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1FBCLKLOST : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1LOCK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1OUTCLK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1OUTREFCLK : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLL1REFCLKLOST : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_QPLLDMONITOR0 : out std_logic_vector(7 downto 0);
+ GTHE4_COMMON_QPLLDMONITOR1 : out std_logic_vector(7 downto 0);
+ GTHE4_COMMON_REFCLKOUTMONITOR0 : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_REFCLKOUTMONITOR1 : out std_logic_vector(0 downto 0);
+ GTHE4_COMMON_RXRECCLK0SEL : out std_logic_vector(1 downto 0);
+ GTHE4_COMMON_RXRECCLK1SEL : out std_logic_vector(1 downto 0);
+ GTHE4_COMMON_SDM0FINALOUT : out std_logic_vector(3 downto 0);
+ GTHE4_COMMON_SDM0TESTDATA : out std_logic_vector(14 downto 0);
+ GTHE4_COMMON_SDM1FINALOUT : out std_logic_vector(3 downto 0);
+ GTHE4_COMMON_SDM1TESTDATA : out std_logic_vector(14 downto 0);
+ GTHE4_COMMON_TCONGPO : out std_logic_vector(9 downto 0);
+ GTHE4_COMMON_TCONRSVDOUT0 : out std_logic_vector(0 downto 0)
+ );
+ end component;
+
+begin
+
+ -- INPUT BUFFER
+ IBUFDS_GTE4_inst : IBUFDS_GTE4
+ generic map (
+ REFCLK_EN_TX_PATH => '0',
+ REFCLK_HROW_CK_SEL => "00",
+ REFCLK_ICNTL_RX => "00"
+ )
+ port map (
+ O => gtrefclk,
+ ODIV2 => open,
+ CEB => '0',
+ I => gtrefclk_p,
+ IB => gtrefclk_n
+ );
+
+
+ -- TRANSCEIVER COMMON BLOCK
+ gthe4_common_wrapper_inst: combpm_gtwizard_gthe4_common_wrapper
+ port map(
+ GTHE4_COMMON_BGBYPASSB => "1",
+ GTHE4_COMMON_BGMONITORENB => "1",
+ GTHE4_COMMON_BGPDB => "1",
+ GTHE4_COMMON_BGRCALOVRD => "11111",
+ GTHE4_COMMON_BGRCALOVRDENB => "1",
+ GTHE4_COMMON_DRPADDR => "0000000000000000",
+ GTHE4_COMMON_DRPCLK => "0",
+ GTHE4_COMMON_DRPDI => "0000000000000000",
+ GTHE4_COMMON_DRPEN => "0",
+ GTHE4_COMMON_DRPWE => "0",
+ GTHE4_COMMON_GTGREFCLK0 => "0",
+ GTHE4_COMMON_GTGREFCLK1 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK00 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK01 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK10 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK11 => "0",
+ GTHE4_COMMON_GTREFCLK00(0) => gtrefclk,
+ GTHE4_COMMON_GTREFCLK01(0) => gtrefclk,
+ GTHE4_COMMON_GTREFCLK10 => "0",
+ GTHE4_COMMON_GTREFCLK11 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK00 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK01 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK10 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK11 => "0",
+ GTHE4_COMMON_PCIERATEQPLL0 => "000",
+ GTHE4_COMMON_PCIERATEQPLL1 => "000",
+ GTHE4_COMMON_PMARSVD0 => "00000000",
+ GTHE4_COMMON_PMARSVD1 => "00000000",
+ GTHE4_COMMON_QPLL0CLKRSVD0 => "0",
+ GTHE4_COMMON_QPLL0CLKRSVD1 => "0",
+ GTHE4_COMMON_QPLL0FBDIV => "00000000",
+ GTHE4_COMMON_QPLL0LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL0LOCKEN => "1",
+ GTHE4_COMMON_QPLL0PD => "0",
+ GTHE4_COMMON_QPLL0REFCLKSEL => "001",
+ GTHE4_COMMON_QPLL0RESET(0) => qpll0reset,
+ GTHE4_COMMON_QPLL1CLKRSVD0 => "0",
+ GTHE4_COMMON_QPLL1CLKRSVD1 => "0",
+ GTHE4_COMMON_QPLL1FBDIV => "00000000",
+ GTHE4_COMMON_QPLL1LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL1LOCKEN => "1",
+ GTHE4_COMMON_QPLL1PD => "0",
+ GTHE4_COMMON_QPLL1REFCLKSEL => "001",
+ GTHE4_COMMON_QPLL1RESET(0) => qpll1reset,
+ GTHE4_COMMON_QPLLRSVD1 => "00000000",
+ GTHE4_COMMON_QPLLRSVD2 => "00000",
+ GTHE4_COMMON_QPLLRSVD3 => "00000",
+ GTHE4_COMMON_QPLLRSVD4 => "00000000",
+ GTHE4_COMMON_RCALENB => "1",
+ GTHE4_COMMON_SDM0DATA => "0000000000000000000000000",
+ GTHE4_COMMON_SDM0RESET => "0",
+ GTHE4_COMMON_SDM0TOGGLE => "0",
+ GTHE4_COMMON_SDM0WIDTH => "00",
+ GTHE4_COMMON_SDM1DATA => "0010001011010000111001010",
+ GTHE4_COMMON_SDM1RESET => "0",
+ GTHE4_COMMON_SDM1TOGGLE => "0",
+ GTHE4_COMMON_SDM1WIDTH => "00",
+ GTHE4_COMMON_TCONGPI => "0000000000",
+ GTHE4_COMMON_TCONPOWERUP => "0",
+ GTHE4_COMMON_TCONRESET => "00",
+ GTHE4_COMMON_TCONRSVDIN1 => "00",
+ GTHE4_COMMON_DRPDO => open,
+ GTHE4_COMMON_DRPRDY => open,
+ GTHE4_COMMON_PMARSVDOUT0 => open,
+ GTHE4_COMMON_PMARSVDOUT1 => open,
+ GTHE4_COMMON_QPLL0FBCLKLOST => open,
+ GTHE4_COMMON_QPLL0LOCK(0) => qpll0lock,
+ GTHE4_COMMON_QPLL0OUTCLK(0) => qpll0outclk,
+ GTHE4_COMMON_QPLL0OUTREFCLK(0) => qpll0refclk,
+ GTHE4_COMMON_QPLL0REFCLKLOST => open,
+ GTHE4_COMMON_QPLL1FBCLKLOST => open,
+ GTHE4_COMMON_QPLL1LOCK(0) => qpll1lock,
+ GTHE4_COMMON_QPLL1OUTCLK(0) => qpll1outclk,
+ GTHE4_COMMON_QPLL1OUTREFCLK(0) => qpll1refclk,
+ GTHE4_COMMON_QPLL1REFCLKLOST => open,
+ GTHE4_COMMON_QPLLDMONITOR0 => open,
+ GTHE4_COMMON_QPLLDMONITOR1 => open,
+ GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
+ GTHE4_COMMON_REFCLKOUTMONITOR1 => open,
+ GTHE4_COMMON_RXRECCLK0SEL => open,
+ GTHE4_COMMON_RXRECCLK1SEL => open,
+ GTHE4_COMMON_SDM0FINALOUT => open,
+ GTHE4_COMMON_SDM0TESTDATA => open,
+ GTHE4_COMMON_SDM1FINALOUT => open,
+ GTHE4_COMMON_SDM1TESTDATA => open,
+ GTHE4_COMMON_TCONGPO => open,
+ GTHE4_COMMON_TCONRSVDOUT0 => open
+ );
+
+end architecture struct;
diff --git a/others/gtwizard_ultrascale_v1_7_gthe4_common.v b/others/gtwizard_ultrascale_v1_7_gthe4_common.v
new file mode 100644
index 0000000000000000000000000000000000000000..3f7c77b6785fdfb4b93f54784175b0d5ad66af9e
--- /dev/null
+++ b/others/gtwizard_ultrascale_v1_7_gthe4_common.v
@@ -0,0 +1,928 @@
+//------------------------------------------------------------------------------
+// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_common #(
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // Parameters relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ // primitive wrapper parameters which override corresponding GTHE4_COMMON primitive parameters
+ parameter [0:0] GTHE4_COMMON_AEN_QPLL0_FBDIV = 1'b1,
+ parameter [0:0] GTHE4_COMMON_AEN_QPLL1_FBDIV = 1'b1,
+ parameter [0:0] GTHE4_COMMON_AEN_SDM0TOGGLE = 1'b0,
+ parameter [0:0] GTHE4_COMMON_AEN_SDM1TOGGLE = 1'b0,
+ parameter [0:0] GTHE4_COMMON_A_SDM0TOGGLE = 1'b0,
+ parameter [8:0] GTHE4_COMMON_A_SDM1DATA_HIGH = 9'b000000000,
+ parameter [15:0] GTHE4_COMMON_A_SDM1DATA_LOW = 16'b0000000000000000,
+ parameter [0:0] GTHE4_COMMON_A_SDM1TOGGLE = 1'b0,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG3 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG4 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG_RSVD = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_COMMON_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_COMMON_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_POR_CFG = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_PPF0_CFG = 16'h0F00,
+ parameter [15:0] GTHE4_COMMON_PPF1_CFG = 16'h0F00,
+ parameter GTHE4_COMMON_QPLL0CLKOUT_RATE = "FULL",
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG0 = 16'h391C,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG1_G3 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG2 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG2_G3 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG3 = 16'h0120,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG4 = 16'h0002,
+ parameter [9:0] GTHE4_COMMON_QPLL0_CP = 10'b0000011111,
+ parameter [9:0] GTHE4_COMMON_QPLL0_CP_G3 = 10'b0000011111,
+ parameter integer GTHE4_COMMON_QPLL0_FBDIV = 66,
+ parameter integer GTHE4_COMMON_QPLL0_FBDIV_G3 = 80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_INIT_CFG0 = 16'h0000,
+ parameter [7:0] GTHE4_COMMON_QPLL0_INIT_CFG1 = 8'h00,
+ parameter [15:0] GTHE4_COMMON_QPLL0_LOCK_CFG = 16'h01E8,
+ parameter [15:0] GTHE4_COMMON_QPLL0_LOCK_CFG_G3 = 16'h21E8,
+ parameter [9:0] GTHE4_COMMON_QPLL0_LPF = 10'b1011111111,
+ parameter [9:0] GTHE4_COMMON_QPLL0_LPF_G3 = 10'b1111111111,
+ parameter [0:0] GTHE4_COMMON_QPLL0_PCI_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP = 1'b0,
+ parameter integer GTHE4_COMMON_QPLL0_REFCLK_DIV = 1,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG0 = 16'h0040,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG2 = 16'h0000,
+ parameter GTHE4_COMMON_QPLL1CLKOUT_RATE = "FULL",
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG0 = 16'h691C,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG1 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG1_G3 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG2 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG2_G3 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG3 = 16'h0120,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG4 = 16'h0002,
+ parameter [9:0] GTHE4_COMMON_QPLL1_CP = 10'b0000011111,
+ parameter [9:0] GTHE4_COMMON_QPLL1_CP_G3 = 10'b0000011111,
+ parameter integer GTHE4_COMMON_QPLL1_FBDIV = 66,
+ parameter integer GTHE4_COMMON_QPLL1_FBDIV_G3 = 80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_INIT_CFG0 = 16'h0000,
+ parameter [7:0] GTHE4_COMMON_QPLL1_INIT_CFG1 = 8'h00,
+ parameter [15:0] GTHE4_COMMON_QPLL1_LOCK_CFG = 16'h01E8,
+ parameter [15:0] GTHE4_COMMON_QPLL1_LOCK_CFG_G3 = 16'h21E8,
+ parameter [9:0] GTHE4_COMMON_QPLL1_LPF = 10'b1011111111,
+ parameter [9:0] GTHE4_COMMON_QPLL1_LPF_G3 = 10'b1111111111,
+ parameter [0:0] GTHE4_COMMON_QPLL1_PCI_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP = 1'b0,
+ parameter integer GTHE4_COMMON_QPLL1_REFCLK_DIV = 1,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR3 = 16'h0000,
+ parameter [1:0] GTHE4_COMMON_RXRECCLKOUT0_SEL = 2'b00,
+ parameter [1:0] GTHE4_COMMON_RXRECCLKOUT1_SEL = 2'b00,
+ parameter [0:0] GTHE4_COMMON_SARC_ENB = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SARC_SEL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_SDM0INITSEED0_0 = 16'b0000000000000000,
+ parameter [8:0] GTHE4_COMMON_SDM0INITSEED0_1 = 9'b000000000,
+ parameter [15:0] GTHE4_COMMON_SDM1INITSEED0_0 = 16'b0000000000000000,
+ parameter [8:0] GTHE4_COMMON_SDM1INITSEED0_1 = 9'b000000000,
+ parameter GTHE4_COMMON_SIM_MODE = "FAST",
+ parameter GTHE4_COMMON_SIM_RESET_SPEEDUP = "TRUE",
+ parameter GTHE4_COMMON_SIM_DEVICE = "ULTRASCALE_PLUS",
+
+ // primitive wrapper parameters which specify GTHE4_COMMON primitive input port default driver values
+ parameter [0:0] GTHE4_COMMON_BGBYPASSB_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGMONITORENB_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGPDB_VAL = 1'b0,
+ parameter [4:0] GTHE4_COMMON_BGRCALOVRD_VAL = 5'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRDENB_VAL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_DRPADDR_VAL = 16'b0,
+ parameter [0:0] GTHE4_COMMON_DRPCLK_VAL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_DRPDI_VAL = 16'b0,
+ parameter [0:0] GTHE4_COMMON_DRPEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPWE_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK1_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK11_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK11_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK11_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_PCIERATEQPLL0_VAL = 3'b0,
+ parameter [2:0] GTHE4_COMMON_PCIERATEQPLL1_VAL = 3'b0,
+ parameter [7:0] GTHE4_COMMON_PMARSVD0_VAL = 8'b0,
+ parameter [7:0] GTHE4_COMMON_PMARSVD1_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD1_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLL0FBDIV_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0PD_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_QPLL0REFCLKSEL_VAL = 3'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD1_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLL1FBDIV_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1PD_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_QPLL1REFCLKSEL_VAL = 3'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1RESET_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLLRSVD1_VAL = 8'b0,
+ parameter [4:0] GTHE4_COMMON_QPLLRSVD2_VAL = 5'b0,
+ parameter [4:0] GTHE4_COMMON_QPLLRSVD3_VAL = 5'b0,
+ parameter [7:0] GTHE4_COMMON_QPLLRSVD4_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_RCALENB_VAL = 1'b0,
+ parameter [24:0] GTHE4_COMMON_SDM0DATA_VAL = 25'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0TOGGLE_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_SDM0WIDTH_VAL = 2'b0,
+ parameter [24:0] GTHE4_COMMON_SDM1DATA_VAL = 25'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1TOGGLE_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_SDM1WIDTH_VAL = 2'b0,
+ parameter [9:0] GTHE4_COMMON_TCONGPI_VAL = 10'b0,
+ parameter [0:0] GTHE4_COMMON_TCONPOWERUP_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRESET_VAL = 2'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRSVDIN1_VAL = 2'b0,
+
+ // primitive wrapper parameters which control GTHE4_COMMON primitive input port tie-off enablement
+ parameter [0:0] GTHE4_COMMON_BGBYPASSB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGMONITORENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGPDB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRDENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPADDR_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPDI_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPWE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PCIERATEQPLL0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PCIERATEQPLL1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PMARSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PMARSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0FBDIV_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0PD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1FBDIV_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1PD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD2_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD3_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD4_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_RCALENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0DATA_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0TOGGLE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0WIDTH_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1DATA_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1TOGGLE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1WIDTH_TIE_EN = 1'b0,
+ parameter [9:0] GTHE4_COMMON_TCONGPI_TIE_EN = 10'b0,
+ parameter [0:0] GTHE4_COMMON_TCONPOWERUP_TIE_EN = 1'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRESET_TIE_EN = 2'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRSVDIN1_TIE_EN = 2'b0
+
+)(
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // Ports relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ // primitive wrapper input ports which can drive corresponding GTHE4_COMMON primitive input ports
+ input wire [ 0:0] GTHE4_COMMON_BGBYPASSB,
+ input wire [ 0:0] GTHE4_COMMON_BGMONITORENB,
+ input wire [ 0:0] GTHE4_COMMON_BGPDB,
+ input wire [ 4:0] GTHE4_COMMON_BGRCALOVRD,
+ input wire [ 0:0] GTHE4_COMMON_BGRCALOVRDENB,
+ input wire [15:0] GTHE4_COMMON_DRPADDR,
+ input wire [ 0:0] GTHE4_COMMON_DRPCLK,
+ input wire [15:0] GTHE4_COMMON_DRPDI,
+ input wire [ 0:0] GTHE4_COMMON_DRPEN,
+ input wire [ 0:0] GTHE4_COMMON_DRPWE,
+ input wire [ 0:0] GTHE4_COMMON_GTGREFCLK0,
+ input wire [ 0:0] GTHE4_COMMON_GTGREFCLK1,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK11,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK11,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK11,
+ input wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL0,
+ input wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL1,
+ input wire [ 7:0] GTHE4_COMMON_PMARSVD0,
+ input wire [ 7:0] GTHE4_COMMON_PMARSVD1,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD0,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD1,
+ input wire [ 7:0] GTHE4_COMMON_QPLL0FBDIV,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0LOCKDETCLK,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0LOCKEN,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0PD,
+ input wire [ 2:0] GTHE4_COMMON_QPLL0REFCLKSEL,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0RESET,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD0,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD1,
+ input wire [ 7:0] GTHE4_COMMON_QPLL1FBDIV,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1LOCKDETCLK,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1LOCKEN,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1PD,
+ input wire [ 2:0] GTHE4_COMMON_QPLL1REFCLKSEL,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1RESET,
+ input wire [ 7:0] GTHE4_COMMON_QPLLRSVD1,
+ input wire [ 4:0] GTHE4_COMMON_QPLLRSVD2,
+ input wire [ 4:0] GTHE4_COMMON_QPLLRSVD3,
+ input wire [ 7:0] GTHE4_COMMON_QPLLRSVD4,
+ input wire [ 0:0] GTHE4_COMMON_RCALENB,
+ input wire [24:0] GTHE4_COMMON_SDM0DATA,
+ input wire [ 0:0] GTHE4_COMMON_SDM0RESET,
+ input wire [ 0:0] GTHE4_COMMON_SDM0TOGGLE,
+ input wire [ 1:0] GTHE4_COMMON_SDM0WIDTH,
+ input wire [24:0] GTHE4_COMMON_SDM1DATA,
+ input wire [ 0:0] GTHE4_COMMON_SDM1RESET,
+ input wire [ 0:0] GTHE4_COMMON_SDM1TOGGLE,
+ input wire [ 1:0] GTHE4_COMMON_SDM1WIDTH,
+ input wire [ 9:0] GTHE4_COMMON_TCONGPI,
+ input wire [ 0:0] GTHE4_COMMON_TCONPOWERUP,
+ input wire [ 1:0] GTHE4_COMMON_TCONRESET,
+ input wire [ 1:0] GTHE4_COMMON_TCONRSVDIN1,
+
+ // primitive wrapper output ports which are driven by corresponding GTHE4_COMMON primitive output ports
+ output wire [15:0] GTHE4_COMMON_DRPDO,
+ output wire [ 0:0] GTHE4_COMMON_DRPRDY,
+ output wire [ 7:0] GTHE4_COMMON_PMARSVDOUT0,
+ output wire [ 7:0] GTHE4_COMMON_PMARSVDOUT1,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0FBCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0LOCK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0OUTCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0OUTREFCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0REFCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1FBCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1LOCK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1OUTCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1OUTREFCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1REFCLKLOST,
+ output wire [ 7:0] GTHE4_COMMON_QPLLDMONITOR0,
+ output wire [ 7:0] GTHE4_COMMON_QPLLDMONITOR1,
+ output wire [ 0:0] GTHE4_COMMON_REFCLKOUTMONITOR0,
+ output wire [ 0:0] GTHE4_COMMON_REFCLKOUTMONITOR1,
+ output wire [ 1:0] GTHE4_COMMON_RXRECCLK0SEL,
+ output wire [ 1:0] GTHE4_COMMON_RXRECCLK1SEL,
+ output wire [ 3:0] GTHE4_COMMON_SDM0FINALOUT,
+ output wire [14:0] GTHE4_COMMON_SDM0TESTDATA,
+ output wire [ 3:0] GTHE4_COMMON_SDM1FINALOUT,
+ output wire [14:0] GTHE4_COMMON_SDM1TESTDATA,
+ output wire [ 9:0] GTHE4_COMMON_TCONGPO,
+ output wire [ 0:0] GTHE4_COMMON_TCONRSVDOUT0
+
+);
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // HDL generation of wiring and instances relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ generate if (1) begin : gthe4_common_gen
+
+ // for each GTHE4_COMMON primitive input port, declare a properly-sized vector
+ wire [ 0:0] GTHE4_COMMON_BGBYPASSB_int;
+ wire [ 0:0] GTHE4_COMMON_BGMONITORENB_int;
+ wire [ 0:0] GTHE4_COMMON_BGPDB_int;
+ wire [ 4:0] GTHE4_COMMON_BGRCALOVRD_int;
+ wire [ 0:0] GTHE4_COMMON_BGRCALOVRDENB_int;
+ wire [15:0] GTHE4_COMMON_DRPADDR_int;
+ wire [ 0:0] GTHE4_COMMON_DRPCLK_int;
+ wire [15:0] GTHE4_COMMON_DRPDI_int;
+ wire [ 0:0] GTHE4_COMMON_DRPEN_int;
+ wire [ 0:0] GTHE4_COMMON_DRPWE_int;
+ wire [ 0:0] GTHE4_COMMON_GTGREFCLK0_int;
+ wire [ 0:0] GTHE4_COMMON_GTGREFCLK1_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK11_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK11_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK11_int;
+ wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL0_int;
+ wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL1_int;
+ wire [ 7:0] GTHE4_COMMON_PMARSVD0_int;
+ wire [ 7:0] GTHE4_COMMON_PMARSVD1_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD0_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD1_int;
+ wire [ 7:0] GTHE4_COMMON_QPLL0FBDIV_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0LOCKEN_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0PD_int;
+ wire [ 2:0] GTHE4_COMMON_QPLL0REFCLKSEL_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0RESET_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD0_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD1_int;
+ wire [ 7:0] GTHE4_COMMON_QPLL1FBDIV_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1LOCKEN_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1PD_int;
+ wire [ 2:0] GTHE4_COMMON_QPLL1REFCLKSEL_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1RESET_int;
+ wire [ 7:0] GTHE4_COMMON_QPLLRSVD1_int;
+ wire [ 4:0] GTHE4_COMMON_QPLLRSVD2_int;
+ wire [ 4:0] GTHE4_COMMON_QPLLRSVD3_int;
+ wire [ 7:0] GTHE4_COMMON_QPLLRSVD4_int;
+ wire [ 0:0] GTHE4_COMMON_RCALENB_int;
+ wire [24:0] GTHE4_COMMON_SDM0DATA_int;
+ wire [ 0:0] GTHE4_COMMON_SDM0RESET_int;
+ wire [ 0:0] GTHE4_COMMON_SDM0TOGGLE_int;
+ wire [ 1:0] GTHE4_COMMON_SDM0WIDTH_int;
+ wire [24:0] GTHE4_COMMON_SDM1DATA_int;
+ wire [ 0:0] GTHE4_COMMON_SDM1RESET_int;
+ wire [ 0:0] GTHE4_COMMON_SDM1TOGGLE_int;
+ wire [ 1:0] GTHE4_COMMON_SDM1WIDTH_int;
+ wire [ 9:0] GTHE4_COMMON_TCONGPI_int;
+ wire [ 0:0] GTHE4_COMMON_TCONPOWERUP_int;
+ wire [ 1:0] GTHE4_COMMON_TCONRESET_int;
+ wire [ 1:0] GTHE4_COMMON_TCONRSVDIN1_int;
+
+ // assign each vector either the corresponding tie-off value or the corresponding input port
+ if (GTHE4_COMMON_BGBYPASSB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGBYPASSB_int = GTHE4_COMMON_BGBYPASSB_VAL;
+ else
+ assign GTHE4_COMMON_BGBYPASSB_int = GTHE4_COMMON_BGBYPASSB;
+
+ if (GTHE4_COMMON_BGMONITORENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGMONITORENB_int = GTHE4_COMMON_BGMONITORENB_VAL;
+ else
+ assign GTHE4_COMMON_BGMONITORENB_int = GTHE4_COMMON_BGMONITORENB;
+
+ if (GTHE4_COMMON_BGPDB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGPDB_int = GTHE4_COMMON_BGPDB_VAL;
+ else
+ assign GTHE4_COMMON_BGPDB_int = GTHE4_COMMON_BGPDB;
+
+ if (GTHE4_COMMON_BGRCALOVRD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGRCALOVRD_int = GTHE4_COMMON_BGRCALOVRD_VAL;
+ else
+ assign GTHE4_COMMON_BGRCALOVRD_int = GTHE4_COMMON_BGRCALOVRD;
+
+ if (GTHE4_COMMON_BGRCALOVRDENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGRCALOVRDENB_int = GTHE4_COMMON_BGRCALOVRDENB_VAL;
+ else
+ assign GTHE4_COMMON_BGRCALOVRDENB_int = GTHE4_COMMON_BGRCALOVRDENB;
+
+ if (GTHE4_COMMON_DRPADDR_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPADDR_int = GTHE4_COMMON_DRPADDR_VAL;
+ else
+ assign GTHE4_COMMON_DRPADDR_int = GTHE4_COMMON_DRPADDR;
+
+ if (GTHE4_COMMON_DRPCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPCLK_int = GTHE4_COMMON_DRPCLK_VAL;
+ else
+ assign GTHE4_COMMON_DRPCLK_int = GTHE4_COMMON_DRPCLK;
+
+ if (GTHE4_COMMON_DRPDI_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPDI_int = GTHE4_COMMON_DRPDI_VAL;
+ else
+ assign GTHE4_COMMON_DRPDI_int = GTHE4_COMMON_DRPDI;
+
+ if (GTHE4_COMMON_DRPEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPEN_int = GTHE4_COMMON_DRPEN_VAL;
+ else
+ assign GTHE4_COMMON_DRPEN_int = GTHE4_COMMON_DRPEN;
+
+ if (GTHE4_COMMON_DRPWE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPWE_int = GTHE4_COMMON_DRPWE_VAL;
+ else
+ assign GTHE4_COMMON_DRPWE_int = GTHE4_COMMON_DRPWE;
+
+ if (GTHE4_COMMON_GTGREFCLK0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTGREFCLK0_int = GTHE4_COMMON_GTGREFCLK0_VAL;
+ else
+ assign GTHE4_COMMON_GTGREFCLK0_int = GTHE4_COMMON_GTGREFCLK0;
+
+ if (GTHE4_COMMON_GTGREFCLK1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTGREFCLK1_int = GTHE4_COMMON_GTGREFCLK1_VAL;
+ else
+ assign GTHE4_COMMON_GTGREFCLK1_int = GTHE4_COMMON_GTGREFCLK1;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK00_int = GTHE4_COMMON_GTNORTHREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK00_int = GTHE4_COMMON_GTNORTHREFCLK00;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK01_int = GTHE4_COMMON_GTNORTHREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK01_int = GTHE4_COMMON_GTNORTHREFCLK01;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK10_int = GTHE4_COMMON_GTNORTHREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK10_int = GTHE4_COMMON_GTNORTHREFCLK10;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK11_int = GTHE4_COMMON_GTNORTHREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK11_int = GTHE4_COMMON_GTNORTHREFCLK11;
+
+ if (GTHE4_COMMON_GTREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK00_int = GTHE4_COMMON_GTREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK00_int = GTHE4_COMMON_GTREFCLK00;
+
+ if (GTHE4_COMMON_GTREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK01_int = GTHE4_COMMON_GTREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK01_int = GTHE4_COMMON_GTREFCLK01;
+
+ if (GTHE4_COMMON_GTREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK10_int = GTHE4_COMMON_GTREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK10_int = GTHE4_COMMON_GTREFCLK10;
+
+ if (GTHE4_COMMON_GTREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK11_int = GTHE4_COMMON_GTREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK11_int = GTHE4_COMMON_GTREFCLK11;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK00_int = GTHE4_COMMON_GTSOUTHREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK00_int = GTHE4_COMMON_GTSOUTHREFCLK00;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK01_int = GTHE4_COMMON_GTSOUTHREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK01_int = GTHE4_COMMON_GTSOUTHREFCLK01;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK10_int = GTHE4_COMMON_GTSOUTHREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK10_int = GTHE4_COMMON_GTSOUTHREFCLK10;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK11_int = GTHE4_COMMON_GTSOUTHREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK11_int = GTHE4_COMMON_GTSOUTHREFCLK11;
+
+ if (GTHE4_COMMON_PCIERATEQPLL0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PCIERATEQPLL0_int = GTHE4_COMMON_PCIERATEQPLL0_VAL;
+ else
+ assign GTHE4_COMMON_PCIERATEQPLL0_int = GTHE4_COMMON_PCIERATEQPLL0;
+
+ if (GTHE4_COMMON_PCIERATEQPLL1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PCIERATEQPLL1_int = GTHE4_COMMON_PCIERATEQPLL1_VAL;
+ else
+ assign GTHE4_COMMON_PCIERATEQPLL1_int = GTHE4_COMMON_PCIERATEQPLL1;
+
+ if (GTHE4_COMMON_PMARSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PMARSVD0_int = GTHE4_COMMON_PMARSVD0_VAL;
+ else
+ assign GTHE4_COMMON_PMARSVD0_int = GTHE4_COMMON_PMARSVD0;
+
+ if (GTHE4_COMMON_PMARSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PMARSVD1_int = GTHE4_COMMON_PMARSVD1_VAL;
+ else
+ assign GTHE4_COMMON_PMARSVD1_int = GTHE4_COMMON_PMARSVD1;
+
+ if (GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0CLKRSVD0_int = GTHE4_COMMON_QPLL0CLKRSVD0_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0CLKRSVD0_int = GTHE4_COMMON_QPLL0CLKRSVD0;
+
+ if (GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0CLKRSVD1_int = GTHE4_COMMON_QPLL0CLKRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0CLKRSVD1_int = GTHE4_COMMON_QPLL0CLKRSVD1;
+
+ if (GTHE4_COMMON_QPLL0FBDIV_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0FBDIV_int = GTHE4_COMMON_QPLL0FBDIV_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0FBDIV_int = GTHE4_COMMON_QPLL0FBDIV;
+
+ if (GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0LOCKDETCLK_int = GTHE4_COMMON_QPLL0LOCKDETCLK_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0LOCKDETCLK_int = GTHE4_COMMON_QPLL0LOCKDETCLK;
+
+ if (GTHE4_COMMON_QPLL0LOCKEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0LOCKEN_int = GTHE4_COMMON_QPLL0LOCKEN_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0LOCKEN_int = GTHE4_COMMON_QPLL0LOCKEN;
+
+ if (GTHE4_COMMON_QPLL0PD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0PD_int = GTHE4_COMMON_QPLL0PD_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0PD_int = GTHE4_COMMON_QPLL0PD;
+
+ if (GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0REFCLKSEL_int = GTHE4_COMMON_QPLL0REFCLKSEL_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0REFCLKSEL_int = GTHE4_COMMON_QPLL0REFCLKSEL;
+
+ if (GTHE4_COMMON_QPLL0RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0RESET_int = GTHE4_COMMON_QPLL0RESET_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0RESET_int = GTHE4_COMMON_QPLL0RESET;
+
+ if (GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1CLKRSVD0_int = GTHE4_COMMON_QPLL1CLKRSVD0_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1CLKRSVD0_int = GTHE4_COMMON_QPLL1CLKRSVD0;
+
+ if (GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1CLKRSVD1_int = GTHE4_COMMON_QPLL1CLKRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1CLKRSVD1_int = GTHE4_COMMON_QPLL1CLKRSVD1;
+
+ if (GTHE4_COMMON_QPLL1FBDIV_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1FBDIV_int = GTHE4_COMMON_QPLL1FBDIV_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1FBDIV_int = GTHE4_COMMON_QPLL1FBDIV;
+
+ if (GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1LOCKDETCLK_int = GTHE4_COMMON_QPLL1LOCKDETCLK_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1LOCKDETCLK_int = GTHE4_COMMON_QPLL1LOCKDETCLK;
+
+ if (GTHE4_COMMON_QPLL1LOCKEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1LOCKEN_int = GTHE4_COMMON_QPLL1LOCKEN_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1LOCKEN_int = GTHE4_COMMON_QPLL1LOCKEN;
+
+ if (GTHE4_COMMON_QPLL1PD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1PD_int = GTHE4_COMMON_QPLL1PD_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1PD_int = GTHE4_COMMON_QPLL1PD;
+
+ if (GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1REFCLKSEL_int = GTHE4_COMMON_QPLL1REFCLKSEL_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1REFCLKSEL_int = GTHE4_COMMON_QPLL1REFCLKSEL;
+
+ if (GTHE4_COMMON_QPLL1RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1RESET_int = GTHE4_COMMON_QPLL1RESET_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1RESET_int = GTHE4_COMMON_QPLL1RESET;
+
+ if (GTHE4_COMMON_QPLLRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD1_int = GTHE4_COMMON_QPLLRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD1_int = GTHE4_COMMON_QPLLRSVD1;
+
+ if (GTHE4_COMMON_QPLLRSVD2_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD2_int = GTHE4_COMMON_QPLLRSVD2_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD2_int = GTHE4_COMMON_QPLLRSVD2;
+
+ if (GTHE4_COMMON_QPLLRSVD3_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD3_int = GTHE4_COMMON_QPLLRSVD3_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD3_int = GTHE4_COMMON_QPLLRSVD3;
+
+ if (GTHE4_COMMON_QPLLRSVD4_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD4_int = GTHE4_COMMON_QPLLRSVD4_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD4_int = GTHE4_COMMON_QPLLRSVD4;
+
+ if (GTHE4_COMMON_RCALENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_RCALENB_int = GTHE4_COMMON_RCALENB_VAL;
+ else
+ assign GTHE4_COMMON_RCALENB_int = GTHE4_COMMON_RCALENB;
+
+ if (GTHE4_COMMON_SDM0DATA_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0DATA_int = GTHE4_COMMON_SDM0DATA_VAL;
+ else
+ assign GTHE4_COMMON_SDM0DATA_int = GTHE4_COMMON_SDM0DATA;
+
+ if (GTHE4_COMMON_SDM0RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0RESET_int = GTHE4_COMMON_SDM0RESET_VAL;
+ else
+ assign GTHE4_COMMON_SDM0RESET_int = GTHE4_COMMON_SDM0RESET;
+
+ if (GTHE4_COMMON_SDM0TOGGLE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0TOGGLE_int = GTHE4_COMMON_SDM0TOGGLE_VAL;
+ else
+ assign GTHE4_COMMON_SDM0TOGGLE_int = GTHE4_COMMON_SDM0TOGGLE;
+
+ if (GTHE4_COMMON_SDM0WIDTH_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0WIDTH_int = GTHE4_COMMON_SDM0WIDTH_VAL;
+ else
+ assign GTHE4_COMMON_SDM0WIDTH_int = GTHE4_COMMON_SDM0WIDTH;
+
+ if (GTHE4_COMMON_SDM1DATA_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1DATA_int = GTHE4_COMMON_SDM1DATA_VAL;
+ else
+ assign GTHE4_COMMON_SDM1DATA_int = GTHE4_COMMON_SDM1DATA;
+
+ if (GTHE4_COMMON_SDM1RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1RESET_int = GTHE4_COMMON_SDM1RESET_VAL;
+ else
+ assign GTHE4_COMMON_SDM1RESET_int = GTHE4_COMMON_SDM1RESET;
+
+ if (GTHE4_COMMON_SDM1TOGGLE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1TOGGLE_int = GTHE4_COMMON_SDM1TOGGLE_VAL;
+ else
+ assign GTHE4_COMMON_SDM1TOGGLE_int = GTHE4_COMMON_SDM1TOGGLE;
+
+ if (GTHE4_COMMON_SDM1WIDTH_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1WIDTH_int = GTHE4_COMMON_SDM1WIDTH_VAL;
+ else
+ assign GTHE4_COMMON_SDM1WIDTH_int = GTHE4_COMMON_SDM1WIDTH;
+
+ if (GTHE4_COMMON_TCONGPI_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONGPI_int = GTHE4_COMMON_TCONGPI_VAL;
+ else
+ assign GTHE4_COMMON_TCONGPI_int = GTHE4_COMMON_TCONGPI;
+
+ if (GTHE4_COMMON_TCONPOWERUP_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONPOWERUP_int = GTHE4_COMMON_TCONPOWERUP_VAL;
+ else
+ assign GTHE4_COMMON_TCONPOWERUP_int = GTHE4_COMMON_TCONPOWERUP;
+
+ if (GTHE4_COMMON_TCONRESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONRESET_int = GTHE4_COMMON_TCONRESET_VAL;
+ else
+ assign GTHE4_COMMON_TCONRESET_int = GTHE4_COMMON_TCONRESET;
+
+ if (GTHE4_COMMON_TCONRSVDIN1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONRSVDIN1_int = GTHE4_COMMON_TCONRSVDIN1_VAL;
+ else
+ assign GTHE4_COMMON_TCONRSVDIN1_int = GTHE4_COMMON_TCONRSVDIN1;
+
+ // generate the GTHE4_COMMON primitive instance, mapping parameters and ports
+ GTHE4_COMMON #(
+ .AEN_QPLL0_FBDIV (GTHE4_COMMON_AEN_QPLL0_FBDIV ),
+ .AEN_QPLL1_FBDIV (GTHE4_COMMON_AEN_QPLL1_FBDIV ),
+ .AEN_SDM0TOGGLE (GTHE4_COMMON_AEN_SDM0TOGGLE ),
+ .AEN_SDM1TOGGLE (GTHE4_COMMON_AEN_SDM1TOGGLE ),
+ .A_SDM0TOGGLE (GTHE4_COMMON_A_SDM0TOGGLE ),
+ .A_SDM1DATA_HIGH (GTHE4_COMMON_A_SDM1DATA_HIGH ),
+ .A_SDM1DATA_LOW (GTHE4_COMMON_A_SDM1DATA_LOW ),
+ .A_SDM1TOGGLE (GTHE4_COMMON_A_SDM1TOGGLE ),
+ .BIAS_CFG0 (GTHE4_COMMON_BIAS_CFG0 ),
+ .BIAS_CFG1 (GTHE4_COMMON_BIAS_CFG1 ),
+ .BIAS_CFG2 (GTHE4_COMMON_BIAS_CFG2 ),
+ .BIAS_CFG3 (GTHE4_COMMON_BIAS_CFG3 ),
+ .BIAS_CFG4 (GTHE4_COMMON_BIAS_CFG4 ),
+ .BIAS_CFG_RSVD (GTHE4_COMMON_BIAS_CFG_RSVD ),
+ .COMMON_CFG0 (GTHE4_COMMON_COMMON_CFG0 ),
+ .COMMON_CFG1 (GTHE4_COMMON_COMMON_CFG1 ),
+ .POR_CFG (GTHE4_COMMON_POR_CFG ),
+ .PPF0_CFG (GTHE4_COMMON_PPF0_CFG ),
+ .PPF1_CFG (GTHE4_COMMON_PPF1_CFG ),
+ .QPLL0CLKOUT_RATE (GTHE4_COMMON_QPLL0CLKOUT_RATE ),
+ .QPLL0_CFG0 (GTHE4_COMMON_QPLL0_CFG0 ),
+ .QPLL0_CFG1 (GTHE4_COMMON_QPLL0_CFG1 ),
+ .QPLL0_CFG1_G3 (GTHE4_COMMON_QPLL0_CFG1_G3 ),
+ .QPLL0_CFG2 (GTHE4_COMMON_QPLL0_CFG2 ),
+ .QPLL0_CFG2_G3 (GTHE4_COMMON_QPLL0_CFG2_G3 ),
+ .QPLL0_CFG3 (GTHE4_COMMON_QPLL0_CFG3 ),
+ .QPLL0_CFG4 (GTHE4_COMMON_QPLL0_CFG4 ),
+ .QPLL0_CP (GTHE4_COMMON_QPLL0_CP ),
+ .QPLL0_CP_G3 (GTHE4_COMMON_QPLL0_CP_G3 ),
+ .QPLL0_FBDIV (GTHE4_COMMON_QPLL0_FBDIV ),
+ .QPLL0_FBDIV_G3 (GTHE4_COMMON_QPLL0_FBDIV_G3 ),
+ .QPLL0_INIT_CFG0 (GTHE4_COMMON_QPLL0_INIT_CFG0 ),
+ .QPLL0_INIT_CFG1 (GTHE4_COMMON_QPLL0_INIT_CFG1 ),
+ .QPLL0_LOCK_CFG (GTHE4_COMMON_QPLL0_LOCK_CFG ),
+ .QPLL0_LOCK_CFG_G3 (GTHE4_COMMON_QPLL0_LOCK_CFG_G3 ),
+ .QPLL0_LPF (GTHE4_COMMON_QPLL0_LPF ),
+ .QPLL0_LPF_G3 (GTHE4_COMMON_QPLL0_LPF_G3 ),
+ .QPLL0_PCI_EN (GTHE4_COMMON_QPLL0_PCI_EN ),
+ .QPLL0_RATE_SW_USE_DRP (GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP),
+ .QPLL0_REFCLK_DIV (GTHE4_COMMON_QPLL0_REFCLK_DIV ),
+ .QPLL0_SDM_CFG0 (GTHE4_COMMON_QPLL0_SDM_CFG0 ),
+ .QPLL0_SDM_CFG1 (GTHE4_COMMON_QPLL0_SDM_CFG1 ),
+ .QPLL0_SDM_CFG2 (GTHE4_COMMON_QPLL0_SDM_CFG2 ),
+ .QPLL1CLKOUT_RATE (GTHE4_COMMON_QPLL1CLKOUT_RATE ),
+ .QPLL1_CFG0 (GTHE4_COMMON_QPLL1_CFG0 ),
+ .QPLL1_CFG1 (GTHE4_COMMON_QPLL1_CFG1 ),
+ .QPLL1_CFG1_G3 (GTHE4_COMMON_QPLL1_CFG1_G3 ),
+ .QPLL1_CFG2 (GTHE4_COMMON_QPLL1_CFG2 ),
+ .QPLL1_CFG2_G3 (GTHE4_COMMON_QPLL1_CFG2_G3 ),
+ .QPLL1_CFG3 (GTHE4_COMMON_QPLL1_CFG3 ),
+ .QPLL1_CFG4 (GTHE4_COMMON_QPLL1_CFG4 ),
+ .QPLL1_CP (GTHE4_COMMON_QPLL1_CP ),
+ .QPLL1_CP_G3 (GTHE4_COMMON_QPLL1_CP_G3 ),
+ .QPLL1_FBDIV (GTHE4_COMMON_QPLL1_FBDIV ),
+ .QPLL1_FBDIV_G3 (GTHE4_COMMON_QPLL1_FBDIV_G3 ),
+ .QPLL1_INIT_CFG0 (GTHE4_COMMON_QPLL1_INIT_CFG0 ),
+ .QPLL1_INIT_CFG1 (GTHE4_COMMON_QPLL1_INIT_CFG1 ),
+ .QPLL1_LOCK_CFG (GTHE4_COMMON_QPLL1_LOCK_CFG ),
+ .QPLL1_LOCK_CFG_G3 (GTHE4_COMMON_QPLL1_LOCK_CFG_G3 ),
+ .QPLL1_LPF (GTHE4_COMMON_QPLL1_LPF ),
+ .QPLL1_LPF_G3 (GTHE4_COMMON_QPLL1_LPF_G3 ),
+ .QPLL1_PCI_EN (GTHE4_COMMON_QPLL1_PCI_EN ),
+ .QPLL1_RATE_SW_USE_DRP (GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP),
+ .QPLL1_REFCLK_DIV (GTHE4_COMMON_QPLL1_REFCLK_DIV ),
+ .QPLL1_SDM_CFG0 (GTHE4_COMMON_QPLL1_SDM_CFG0 ),
+ .QPLL1_SDM_CFG1 (GTHE4_COMMON_QPLL1_SDM_CFG1 ),
+ .QPLL1_SDM_CFG2 (GTHE4_COMMON_QPLL1_SDM_CFG2 ),
+ .RSVD_ATTR0 (GTHE4_COMMON_RSVD_ATTR0 ),
+ .RSVD_ATTR1 (GTHE4_COMMON_RSVD_ATTR1 ),
+ .RSVD_ATTR2 (GTHE4_COMMON_RSVD_ATTR2 ),
+ .RSVD_ATTR3 (GTHE4_COMMON_RSVD_ATTR3 ),
+ .RXRECCLKOUT0_SEL (GTHE4_COMMON_RXRECCLKOUT0_SEL ),
+ .RXRECCLKOUT1_SEL (GTHE4_COMMON_RXRECCLKOUT1_SEL ),
+ .SARC_ENB (GTHE4_COMMON_SARC_ENB ),
+ .SARC_SEL (GTHE4_COMMON_SARC_SEL ),
+ .SDM0INITSEED0_0 (GTHE4_COMMON_SDM0INITSEED0_0 ),
+ .SDM0INITSEED0_1 (GTHE4_COMMON_SDM0INITSEED0_1 ),
+ .SDM1INITSEED0_0 (GTHE4_COMMON_SDM1INITSEED0_0 ),
+ .SDM1INITSEED0_1 (GTHE4_COMMON_SDM1INITSEED0_1 ),
+ .SIM_MODE (GTHE4_COMMON_SIM_MODE ),
+ .SIM_RESET_SPEEDUP (GTHE4_COMMON_SIM_RESET_SPEEDUP ),
+ .SIM_DEVICE (GTHE4_COMMON_SIM_DEVICE )
+ ) GTHE4_COMMON_PRIM_INST (
+ .BGBYPASSB (GTHE4_COMMON_BGBYPASSB_int [ 0:0]),
+ .BGMONITORENB (GTHE4_COMMON_BGMONITORENB_int [ 0:0]),
+ .BGPDB (GTHE4_COMMON_BGPDB_int [ 0:0]),
+ .BGRCALOVRD (GTHE4_COMMON_BGRCALOVRD_int [ 4:0]),
+ .BGRCALOVRDENB (GTHE4_COMMON_BGRCALOVRDENB_int [ 0:0]),
+ .DRPADDR (GTHE4_COMMON_DRPADDR_int [15:0]),
+ .DRPCLK (GTHE4_COMMON_DRPCLK_int [ 0:0]),
+ .DRPDI (GTHE4_COMMON_DRPDI_int [15:0]),
+ .DRPEN (GTHE4_COMMON_DRPEN_int [ 0:0]),
+ .DRPWE (GTHE4_COMMON_DRPWE_int [ 0:0]),
+ .GTGREFCLK0 (GTHE4_COMMON_GTGREFCLK0_int [ 0:0]),
+ .GTGREFCLK1 (GTHE4_COMMON_GTGREFCLK1_int [ 0:0]),
+ .GTNORTHREFCLK00 (GTHE4_COMMON_GTNORTHREFCLK00_int [ 0:0]),
+ .GTNORTHREFCLK01 (GTHE4_COMMON_GTNORTHREFCLK01_int [ 0:0]),
+ .GTNORTHREFCLK10 (GTHE4_COMMON_GTNORTHREFCLK10_int [ 0:0]),
+ .GTNORTHREFCLK11 (GTHE4_COMMON_GTNORTHREFCLK11_int [ 0:0]),
+ .GTREFCLK00 (GTHE4_COMMON_GTREFCLK00_int [ 0:0]),
+ .GTREFCLK01 (GTHE4_COMMON_GTREFCLK01_int [ 0:0]),
+ .GTREFCLK10 (GTHE4_COMMON_GTREFCLK10_int [ 0:0]),
+ .GTREFCLK11 (GTHE4_COMMON_GTREFCLK11_int [ 0:0]),
+ .GTSOUTHREFCLK00 (GTHE4_COMMON_GTSOUTHREFCLK00_int [ 0:0]),
+ .GTSOUTHREFCLK01 (GTHE4_COMMON_GTSOUTHREFCLK01_int [ 0:0]),
+ .GTSOUTHREFCLK10 (GTHE4_COMMON_GTSOUTHREFCLK10_int [ 0:0]),
+ .GTSOUTHREFCLK11 (GTHE4_COMMON_GTSOUTHREFCLK11_int [ 0:0]),
+ .PCIERATEQPLL0 (GTHE4_COMMON_PCIERATEQPLL0_int [ 2:0]),
+ .PCIERATEQPLL1 (GTHE4_COMMON_PCIERATEQPLL1_int [ 2:0]),
+ .PMARSVD0 (GTHE4_COMMON_PMARSVD0_int [ 7:0]),
+ .PMARSVD1 (GTHE4_COMMON_PMARSVD1_int [ 7:0]),
+ .QPLL0CLKRSVD0 (GTHE4_COMMON_QPLL0CLKRSVD0_int [ 0:0]),
+ .QPLL0CLKRSVD1 (GTHE4_COMMON_QPLL0CLKRSVD1_int [ 0:0]),
+ .QPLL0FBDIV (GTHE4_COMMON_QPLL0FBDIV_int [ 7:0]),
+ .QPLL0LOCKDETCLK (GTHE4_COMMON_QPLL0LOCKDETCLK_int [ 0:0]),
+ .QPLL0LOCKEN (GTHE4_COMMON_QPLL0LOCKEN_int [ 0:0]),
+ .QPLL0PD (GTHE4_COMMON_QPLL0PD_int [ 0:0]),
+ .QPLL0REFCLKSEL (GTHE4_COMMON_QPLL0REFCLKSEL_int [ 2:0]),
+ .QPLL0RESET (GTHE4_COMMON_QPLL0RESET_int [ 0:0]),
+ .QPLL1CLKRSVD0 (GTHE4_COMMON_QPLL1CLKRSVD0_int [ 0:0]),
+ .QPLL1CLKRSVD1 (GTHE4_COMMON_QPLL1CLKRSVD1_int [ 0:0]),
+ .QPLL1FBDIV (GTHE4_COMMON_QPLL1FBDIV_int [ 7:0]),
+ .QPLL1LOCKDETCLK (GTHE4_COMMON_QPLL1LOCKDETCLK_int [ 0:0]),
+ .QPLL1LOCKEN (GTHE4_COMMON_QPLL1LOCKEN_int [ 0:0]),
+ .QPLL1PD (GTHE4_COMMON_QPLL1PD_int [ 0:0]),
+ .QPLL1REFCLKSEL (GTHE4_COMMON_QPLL1REFCLKSEL_int [ 2:0]),
+ .QPLL1RESET (GTHE4_COMMON_QPLL1RESET_int [ 0:0]),
+ .QPLLRSVD1 (GTHE4_COMMON_QPLLRSVD1_int [ 7:0]),
+ .QPLLRSVD2 (GTHE4_COMMON_QPLLRSVD2_int [ 4:0]),
+ .QPLLRSVD3 (GTHE4_COMMON_QPLLRSVD3_int [ 4:0]),
+ .QPLLRSVD4 (GTHE4_COMMON_QPLLRSVD4_int [ 7:0]),
+ .RCALENB (GTHE4_COMMON_RCALENB_int [ 0:0]),
+ .SDM0DATA (GTHE4_COMMON_SDM0DATA_int [24:0]),
+ .SDM0RESET (GTHE4_COMMON_SDM0RESET_int [ 0:0]),
+ .SDM0TOGGLE (GTHE4_COMMON_SDM0TOGGLE_int [ 0:0]),
+ .SDM0WIDTH (GTHE4_COMMON_SDM0WIDTH_int [ 1:0]),
+ .SDM1DATA (GTHE4_COMMON_SDM1DATA_int [24:0]),
+ .SDM1RESET (GTHE4_COMMON_SDM1RESET_int [ 0:0]),
+ .SDM1TOGGLE (GTHE4_COMMON_SDM1TOGGLE_int [ 0:0]),
+ .SDM1WIDTH (GTHE4_COMMON_SDM1WIDTH_int [ 1:0]),
+ .TCONGPI (GTHE4_COMMON_TCONGPI_int [ 9:0]),
+ .TCONPOWERUP (GTHE4_COMMON_TCONPOWERUP_int [ 0:0]),
+ .TCONRESET (GTHE4_COMMON_TCONRESET_int [ 1:0]),
+ .TCONRSVDIN1 (GTHE4_COMMON_TCONRSVDIN1_int [ 1:0]),
+
+ .DRPDO (GTHE4_COMMON_DRPDO [15:0]),
+ .DRPRDY (GTHE4_COMMON_DRPRDY [ 0:0]),
+ .PMARSVDOUT0 (GTHE4_COMMON_PMARSVDOUT0 [ 7:0]),
+ .PMARSVDOUT1 (GTHE4_COMMON_PMARSVDOUT1 [ 7:0]),
+ .QPLL0FBCLKLOST (GTHE4_COMMON_QPLL0FBCLKLOST [ 0:0]),
+ .QPLL0LOCK (GTHE4_COMMON_QPLL0LOCK [ 0:0]),
+ .QPLL0OUTCLK (GTHE4_COMMON_QPLL0OUTCLK [ 0:0]),
+ .QPLL0OUTREFCLK (GTHE4_COMMON_QPLL0OUTREFCLK [ 0:0]),
+ .QPLL0REFCLKLOST (GTHE4_COMMON_QPLL0REFCLKLOST [ 0:0]),
+ .QPLL1FBCLKLOST (GTHE4_COMMON_QPLL1FBCLKLOST [ 0:0]),
+ .QPLL1LOCK (GTHE4_COMMON_QPLL1LOCK [ 0:0]),
+ .QPLL1OUTCLK (GTHE4_COMMON_QPLL1OUTCLK [ 0:0]),
+ .QPLL1OUTREFCLK (GTHE4_COMMON_QPLL1OUTREFCLK [ 0:0]),
+ .QPLL1REFCLKLOST (GTHE4_COMMON_QPLL1REFCLKLOST [ 0:0]),
+ .QPLLDMONITOR0 (GTHE4_COMMON_QPLLDMONITOR0 [ 7:0]),
+ .QPLLDMONITOR1 (GTHE4_COMMON_QPLLDMONITOR1 [ 7:0]),
+ .REFCLKOUTMONITOR0 (GTHE4_COMMON_REFCLKOUTMONITOR0 [ 0:0]),
+ .REFCLKOUTMONITOR1 (GTHE4_COMMON_REFCLKOUTMONITOR1 [ 0:0]),
+ .RXRECCLK0SEL (GTHE4_COMMON_RXRECCLK0SEL [ 1:0]),
+ .RXRECCLK1SEL (GTHE4_COMMON_RXRECCLK1SEL [ 1:0]),
+ .SDM0FINALOUT (GTHE4_COMMON_SDM0FINALOUT [ 3:0]),
+ .SDM0TESTDATA (GTHE4_COMMON_SDM0TESTDATA [14:0]),
+ .SDM1FINALOUT (GTHE4_COMMON_SDM1FINALOUT [ 3:0]),
+ .SDM1TESTDATA (GTHE4_COMMON_SDM1TESTDATA [14:0]),
+ .TCONGPO (GTHE4_COMMON_TCONGPO [ 9:0]),
+ .TCONRSVDOUT0 (GTHE4_COMMON_TCONRSVDOUT0 [ 0:0])
+
+ );
+
+ end
+ endgenerate
+
+
+endmodule
diff --git a/tcl/bloc_synthesis.tcl b/tcl/bloc_synthesis.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c48220a6608c625e4d9918affc845fee66b5e805
--- /dev/null
+++ b/tcl/bloc_synthesis.tcl
@@ -0,0 +1,20 @@
+# Source metadata
+source ./tcl/metadata.tcl
+
+# Create project
+create_project synth_project -part ${part} -in_memory
+set_property source_mgmt_mode All [current_project]
+
+set_property IP_REPO_PATHS . [current_fileset]
+update_ip_catalog
+
+# Create instance of the IP
+create_ip -vendor ${vlnv_vendor} -library "user" -name "combpm" -module_name combpm_0
+
+# Generate output products
+#generate_target all [get_ips combpm_0]
+
+# Try synthesis
+synth_ip [get_ips combpm_0]
+
+close_project