Newer
Older
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
library UNISIM;
use UNISIM.vcomponents.all;
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
entity combpm_gtwrapper is
port(
-- 100MHz clock, main ref clock
clk_100 : in std_logic;
-- Usrclock for data transfer
usrclk : out std_logic;
-- Async reset active low
rst_n : in std_logic;
-- Differential reference clock inputs and buffered output
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
mgtrefclk : out std_logic;
-- SFP interfaces
sfp_txp : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_txn : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rxp : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rxn : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_rx_los : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_mod_abs : in std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_tx_disable : out std_logic_vector(C_NUM_CHAN-1 downto 0);
sfp_tx_fault : in std_logic_vector(C_NUM_CHAN-1 downto 0);
-- GT interfaces
gt_datarx : out std_logic_vector(16*C_NUM_CHAN-1 downto 0);
gt_datatx : in std_logic_vector(16*C_NUM_CHAN-1 downto 0);
gt_powergood : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_qplllock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxbyteisaligned : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxbyterealign : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcommadet : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcdrlock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
gt_txfault : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxlos : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_modabs : out std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rstall : in std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_rxcommadeten : in std_logic_vector(C_NUM_CHAN-1 downto 0);
gt_txdisable : in std_logic_vector(C_NUM_CHAN-1 downto 0)
);
end entity combpm_gtwrapper;
architecture struct of combpm_gtwrapper is
--------------------------------
-- INTERFACE PORT ASSOCIATION --
--------------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
------------------------
-- SIGNAL DECLARATION --
------------------------
signal txclkactive : std_logic;
signal rxclkactive : std_logic;
signal rstall : std_logic;
signal txresetdone : std_logic;
signal rxresetdone : std_logic;
signal qplllock : std_logic;
signal ref_clk : std_logic;
begin
---------------------
-- DIFF CLK BUFFER --
---------------------
ibufd_clkref_inst: IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => ref_clk,
ODIV2 => open,
CEB => '0',
I => mgtrefclk_p,
IB => mgtrefclk_n
);
-- Connect to output port
mgtrefclk <= ref_clk;
-----------------
-- MAP SIGNALS --
-----------------
g_map_sigs:for I in 0 to C_NUM_CHAN-1 generate
gt_txclkactive(I) <= txclkactive;
gt_rxclkactive(I) <= rxclkactive;
gt_txresetdone(I) <= txresetdone;
gt_rxresetdone(I) <= rxresetdone;
gt_qplllock(I) <= qplllock;
rstall <= or_reduce(gt_rstall);
gt_txfault <= sfp_tx_fault;
gt_rxlos <= sfp_rx_los;
gt_modabs <= sfp_mod_abs;
sfp_tx_disable <= gt_txdisable;
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
--------------------------
-- TRANSCEIVER INSTANCE --
--------------------------
gtwiz_inst: combpm_gtwizard
PORT MAP (
gtwiz_userclk_tx_reset_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open,
gtwiz_userclk_tx_active_out(0) => txclkactive,
gtwiz_userclk_rx_reset_in => "0",
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userclk_rx_usrclk2_out => open,
gtwiz_userclk_rx_active_out(0) => rxclkactive,
gtwiz_reset_clk_freerun_in(0) => clk_100,
gtwiz_reset_all_in(0) => rstall,
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
gtwiz_reset_rx_datapath_in => "0",
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out(0) => txresetdone,
gtwiz_reset_rx_done_out(0) => rxresetdone,
gtwiz_userdata_tx_in => gt_datatx,
gtwiz_userdata_rx_out => gt_datarx,
gtrefclk01_in(0) => ref_clk,
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
qpll1outclk_out => open,
qpll1outrefclk_out => open,
gthrxn_in => sfp_rxn,
gthrxp_in => sfp_rxp,
rxbufreset_in => (others => '0'),
rx8b10ben_in => (others => '1'),
rxcommadeten_in => gt_rxcommadeten,
rxmcommaalignen_in => (others => '1'),
rxpcommaalignen_in => (others => '1'),
tx8b10ben_in => (others => '1'),
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gthtxn_out => sfp_txn,
gthtxp_out => sfp_txp,
gtpowergood_out => gt_powergood,
rxbufstatus_out => open,
rxbyteisaligned_out => gt_rxbyteisaligned,
rxbyterealign_out => gt_rxbyterealign,
rxclkcorcnt_out => open,
rxcommadet_out => gt_rxcommadet,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open
);
end architecture struct;