combpm.rdl

`include "combpm.vh" // Auto generated from FWK

addrmap combpm {

    desyrdl_generate_hdl = true;
    desyrdl_interface = "AXI4L";

    name="BPM protocol decoder controller";

    reg {
        desc="Module identifier.";
        field {hw=w;sw=r;} data[32];
    } ID;

    reg {
        desc="Module version.";
        field {hw=w;sw=r;} data[32];
    } VERSION;

    reg {
        desc="SFP module status";
        desyrdl_data_type="bitfields";

        field {desc="RX lost signal";hw=w;sw=r;
        } RXLOS;
        field {desc="Module is absent";hw=w;sw=r;
        } MODABS;
    } SFP;

    reg {
        desc="GT transceivers status and control";
        desyrdl_data_type="bitfields";

        field {desc="Powergood signal";hw=w;sw=r;
        } POWERGOOD;

        field {desc="PLL lock signal";hw=w;sw=r;
        } QPLLLOCK;

        field {desc="RX clk active signal";hw=w;sw=r;
        } RXCLKACTIVE;

        field {desc="RX CDR lock signal";hw=w;sw=r;
        } RXCDRLOCK;

        field {desc="RX reset done signal";hw=w;sw=r;
        } RXRESETDONE;

        field {desc="RX byte is aligned signal";hw=w;sw=r;
        } RXBYTEISALIGNED;

        field {desc="RX byte realign signal";hw=w;sw=r;
        } RXBYTEREALIGN;

        field {desc="RX comma detected signal";hw=w;sw=r;
        } RXCOMMADET;

        field {desc="RX comma detection enable signal";hw=r;sw=rw;
        } RXCOMMADETEN = 1;

        field {desc="Reset RX datapath";hw=r;sw=rw;
        } RXRSTDATAPATH = 1;

        field {desc="Reset RX PLL and datapath";hw=r;sw=rw;
        } RXRSTPLLDATAPATH = 1;

    } GT;

    reg {
        desc="BPM protocol status and control";
        desyrdl_data_type="bitfields";

        field {desc="Frame error";hw=w;sw=r;
        } FRAMEERROR;

        field {desc="Sequence frame count mismatch";hw=w;sw=r;
        } SEQFRAMECNTERROR;

        field {desc="Sequence frame discontinuity";hw=w;sw=r;
        } SEQFRAMEDISCONT;

        field {desc="Soft reset";hw=r;sw=rw;
        } SOFTRESET;

    } PROTOCOL;

    reg {
        desc="BPM protocol valid frame counters";
        field {hw=w;sw=r;} data[32];
    } VALIDFRAMECNT;

    reg {
        desc="BPM protocol invalid frame counters";
        field {hw=w;sw=r;} data[32];
    } INVALIDFRAMECNT;

    reg {
        desc="BPM protocol valid frame rate";
        field {hw=w;sw=r;} data[32];
    } VALIDFRAMERATE;

    reg {
        desc="BPM protocol invalid frame rate";
        field {hw=w;sw=r;} data[32];
    } INVALIDFRAMERATE;

    reg {
        desc="BPM protocol frame sequence";
        field {hw=w;sw=r;} data[16];
    } FRAMESEQ;

    external mem {
        desc = "BPM filter table";
        memwidth = 8;
        mementries = 2**`C_W_ADDR_TABLE;
    } TABLE;

};