Skip to content
Snippets Groups Projects
Commit 042d6a09 authored by BRONES Romain's avatar BRONES Romain
Browse files

fix: Remove multadd from scaler

* This fixes the possible latency mismatch between simulation and
  reality.
* Use RTL implementation.
parent 04d45d21
No related branches found
No related tags found
No related merge requests found
......@@ -36,7 +36,7 @@ architecture rtl of MultiScaler is
-- CONSTANT
constant C_PIPE_LEN : natural := 5;
constant C_PIPE_LEN : natural := 3;
-- Array for TIDX pipeline delay
type t_tidx_array is array(C_PIPE_LEN-1 downto 0) of std_logic_vector(C_W_TIDX-1 downto 0);
......@@ -53,6 +53,10 @@ architecture rtl of MultiScaler is
signal scale : std_logic_vector(C_W_SCALE-1 downto 0);
signal offset : std_logic_vector(C_W_OFFSET-1 downto 0);
signal mult : signed(C_W_SCALE+C_W_SINE-1 downto 0);
signal pad_offset : std_logic_vector(C_W_OFFSET+C_W_PADDING-1 downto 0);
signal madd : signed(C_W_SCALE+C_W_SINE-1 downto 0);
signal wave : std_logic_vector(C_W_SIG-1 downto 0);
begin
......@@ -111,19 +115,21 @@ begin
---------------------
-- MULTPLY AND ADD --
---------------------
inst_multadd : pscgen_multadd
port map (
clk => clk,
ce => '1',
sclr => '0',
a => r_sine,
b => scale,
c(C_W_OFFSET+C_W_PADDING-1 downto C_W_PADDING) => r_offset,
c(C_W_PADDING-1 downto 0) => (others => '0'),
subtract => '0',
p => wave,
pcout => open
);
pad_offset(C_W_OFFSET+C_W_PADDING-1 downto C_W_PADDING) <= r_offset;
pad_offset(C_W_PADDING-1 downto 0) <= (others => '0');
p_multadd:process(clk, rstn)
begin
if rstn = '0' then
mult <= (others => '0');
madd <= (others => '0');
elsif rising_edge(clk) then
mult <= signed(r_sine) * signed(scale);
madd <= mult + signed(pad_offset);
end if;
end process;
wave <= std_logic_vector(madd(C_W_SINE+C_W_SCALE-1 downto C_W_PADDING));
--------------
-- PORT OUT --
......
......@@ -25,18 +25,4 @@ package pkg_pscgen_gen_ip is
END COMPONENT;
COMPONENT pscgen_multadd
PORT (
CLK : IN STD_LOGIC;
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(C_W_SINE-1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(C_W_SCALE-1 DOWNTO 0);
C : IN STD_LOGIC_VECTOR(C_W_OFFSET+C_W_PADDING-1 DOWNTO 0);
SUBTRACT : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(C_W_SINE+C_W_SCALE-1 DOWNTO C_W_PADDING);
PCOUT : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
end package;
......@@ -41,7 +41,7 @@ end entity top_pscgen;
architecture struct of top_pscgen is
constant C_DELAY : natural := 14;
constant C_DELAY : natural := 12;
type aslv is array(0 to C_DELAY-1) of std_logic_vector(G_W_TUSER+C_W_VALUE-1 downto 0);
signal rst : std_logic;
......
......@@ -39,35 +39,3 @@ export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
## ------------------------------------- ##
## Multiply adder
## ------------------------------------- ##
set ipName "pscgen_multadd"
set padding [expr $Config(C_W_SINE) + $Config(C_W_SCALE) - $Config(C_W_SIG)]
set xcipath [create_ip \
-name xbip_multadd \
-vendor xilinx.com \
-library ip -version 3.0 \
-module_name $ipName]
set_property -dict [list \
CONFIG.c_a_type {0} \
CONFIG.c_b_type {1} \
CONFIG.c_c_type {0} \
CONFIG.c_use_pcin {false} \
CONFIG.c_a_width $Config(C_W_SINE) \
CONFIG.c_b_width $Config(C_W_SCALE) \
CONFIG.c_c_width [expr $Config(C_W_OFFSET) + $padding] \
CONFIG.c_out_high [expr $Config(C_W_SINE) + $Config(C_W_SCALE)-1] \
CONFIG.c_out_low $padding \
CONFIG.c_c_latency {-1} \
] [get_ips $ipName]
generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment